尤瑟斯斯塔
yosys sta (2024-03-19, Verilog, 0KB, 下载0次)
VLSI设计前端加后端，，
VLSI-Design-FrontEnd-plus-BackEnd,, (2018-05-08, Verilog, 0KB, 下载0次)
牛客网刷题记录,
Niuke.com question brushing record, (2023-08-19, Verilog, 0KB, 下载0次)
奈维MIPS，，
NaiveMIPS,, (2015-12-22, Verilog, 0KB, 下载0次)
美联客XILINX FPGA初级教程，对新手很友好详细，错别字请自行脑补。
The English explanation is useless and cannot be written out. Please ignore this paragraph.thank you. (2021-01-11, Verilog, 5745KB, 下载2次)
米联客2020版FPGA课程(MIG DDR篇)-K7
FPGA course 2020 (MIG DDR) - KINTEX 7 (2020-11-09, Verilog, 3180KB, 下载30次)
verilog语言半加器全加器好好看看吧希望对大家有用
Verilog language, half adder, full adder. Have a look. I hope it will be useful to you. (2019-10-28, Verilog, 24KB, 下载0次)
AES加解密算法的Verilog代码，亲测有用
Verilog Code of AES Encryption and Decryption Algorithms (2019-06-24, Verilog, 417KB, 下载12次)
半加器实现，简单的半加器，作为新手实验用
Semi-adder implementation, simple semi-adder, as a novice experiment (2019-06-12, Verilog, 2960KB, 下载6次)
实现了4位半加器的verilog HDL代码
Implementation of Verilog code for 4-bit semi-adde (2019-06-10, Verilog, 252KB, 下载0次)
转帖：AES的简单加解密模块。。。。。。。。。。。。
A Simple Encryption and Decryption Module of AES (2019-04-10, Verilog, 11KB, 下载3次)
1. 利用一位半加器设计八位全加器
2. 进行功能仿真
1. Design of an eight-bit full adder by using a one-and-a-half adder
2. Functional simulation (2019-03-22, Verilog, 678KB, 下载0次)
拉扎维的射频微电子书籍，英文原版，适合初学模拟射频集成电路设计者
Razavi's Radio Frequency Microelectronics Book, English Original, Suitable for Analog Radio Frequency Integrated Circuit Designers (2019-01-21, Verilog, 7475KB, 下载2次)
就是用FPGA写的音频加嵌模块。代码很多慢慢看
it is Using FPGA to write audio module. (2018-10-12, Verilog, 63KB, 下载3次)
利用Verilog语言编写的，在vivado环境下带进位标志的全加器的工程文件与Testbench
Engineering files and Testbench of the full adder with the carry mark in vivado environment written by Verilog language (2018-08-06, Verilog, 258KB, 下载3次)
俄罗斯方块用vga实现 用Verilog代码实现
Tetris is implemented by VGA and implemented by Verilog code. (2018-06-21, Verilog, 18581KB, 下载8次)
aes加解密算法源代码及testbench平台
AES source code and testbench (2018-06-08, Verilog, 84KB, 下载2次)
通过连续调用半加器组成一位全加器，再次调用一位全加器组成4位全加器。对初学者有一定的指导作用。
Through the continuous call half adder of a full adder, called again of a full adder four full adder. For beginners have a certain guiding role. (2018-05-28, Verilog, 1975KB, 下载0次)
led时序仿真加功能仿真时序仿真加功能仿真
时序仿真加功能仿真
Timing simulation plus function simulation
Timing simulation plus function simulation (2017-10-10, Verilog, 2934KB, 下载1次)
用半加器搭建全加器 使用Verilog语言
Using a half adder to build a full adder, using the Verilog language (2017-09-18, Verilog, 274KB, 下载1次)