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[VHDL/FPGA/Verilog] UART_fpga

普拉蒂加巴斯3
Práctica Basys 3 (2022-04-05, HTML, 54KB, 下载0次)

http://www.pudn.com/Download/item/id/1649097801354095.html

[VHDL/FPGA/Verilog] galapagos

加拉帕戈斯，，
galapagos,, (2019-05-09, C++, 5418KB, 下载0次)

http://www.pudn.com/Download/item/id/1557393362194175.html

[VHDL/FPGA/Verilog] 米联客2020版FPGA课程(MIG DDR篇)-K7

米联客2020版FPGA课程(MIG DDR篇)-K7
FPGA course 2020 (MIG DDR) - KINTEX 7 (2020-11-09, Verilog, 3180KB, 下载30次)

http://www.pudn.com/Download/item/id/1604936664539574.html

[VHDL/FPGA/Verilog] 全加器代码

VHDL基础——全加器电路的实现（使用半加器）
VHDL foundation -- the realization of full adder circuit (using half adder) (2020-06-08, VHDL, 139KB, 下载1次)

http://www.pudn.com/Download/item/id/1591622952199775.html

[VHDL/FPGA/Verilog] adder_design_systemc

一个简单的半加器和全加器systemc实现。
A simple half adder and full adder SystemC implementation. (2018-06-08, LINUX, 1KB, 下载0次)

http://www.pudn.com/Download/item/id/1528421681654940.html

[VHDL/FPGA/Verilog] ADDR

8位全加器，包括半加器verilog文件，全加器verilog文件，8位全加器verilog文件，和8位全加器测试testbench文件
8 full adder, including half adder, full adder Verilog file, Verilog file, 8 full adder Verilog files, and 8 full adder test testbench file (2016-04-10, VHDL, 138KB, 下载3次)

http://www.pudn.com/Download/item/id/1460301241647297.html

[VHDL/FPGA/Verilog] quanjia

一位全加器一位全加器一位全加器一位全加器
A full adder a full adder a full adder a full adder (2014-05-08, VHDL, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/2534771.html

[VHDL/FPGA/Verilog] adder4

使用层次化建模的方法再quartus下实现的4位全加器。包括半加器，一位全加器和四位全加器，并进行了仿真。
This file is used for learners to learn verilog. (2014-05-07, VHDL, 288KB, 下载3次)

http://www.pudn.com/Download/item/id/2533563.html

[VHDL/FPGA/Verilog] FT3_crc

FT3发送程序加CRC校验,曼彻斯特编码
FT3 sender plus CRC, Manchester coding (2014-01-03, VHDL, 3230KB, 下载44次)

http://www.pudn.com/Download/item/id/2442467.html

[VHDL/FPGA/Verilog] fulladd4

全加器代码和测试激励文件，优化的全加器，占用FPGA资源少
Full adder code and test incentives (2013-10-26, VHDL, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/2383879.html

[VHDL/FPGA/Verilog] scipydoc

FFT IFFT 转换波形处理加窗等信号处理非常好的书
FFT IFFT conversion waveform processing windowed signal processing a very good book (2012-11-02, matlab, 8192KB, 下载18次)

http://www.pudn.com/Download/item/id/2035020.html

[VHDL/FPGA/Verilog] full_adder

一位全加器工程，用xilinx ISE设计，供初学者学习
A full adder works, the ISE design with xilinx for beginners to learn (2012-06-24, VHDL, 161KB, 下载27次)

http://www.pudn.com/Download/item/id/1921486.html

[VHDL/FPGA/Verilog] half_adder

半加器用verilog语言编写一个半加器，测试结果正确。
half adder (2012-04-23, VHDL, 1KB, 下载8次)

http://www.pudn.com/Download/item/id/1841038.html

[VHDL/FPGA/Verilog] 8f_adder

8位全加器实现8位全加器，先半加器后一位全加器，最后8位全加器
eight add eight add eight add eight add eight add (2011-12-05, VHDL, 2KB, 下载4次)

http://www.pudn.com/Download/item/id/1721435.html

[VHDL/FPGA/Verilog] paomadeng

跑马灯代码阿斯好说的卡上接电话卡结舌杜口京哈蜀客多积货按时间dha空手道会卡水的空间has快结婚ask接电话
good VHDL code asdhkashdkajshdkahskdjhaskjdhkash jkasdhkajsdh akjsdh ajkshd kajshd asjdh kajdh (2011-08-19, VHDL, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/1626525.html

[VHDL/FPGA/Verilog] adder

完成8位全加器功能，从最底层的半加器到1位全加器在到8位全加器的完整设计
adder (2010-05-19, VHDL, 392KB, 下载5次)

http://www.pudn.com/Download/item/id/1179245.html

[VHDL/FPGA/Verilog] halfadder

实现全加器的不可或缺的东西，半加器，功能就是为了全加器做好准备
halfadder (2009-04-27, VHDL, 2KB, 下载3次)

http://www.pudn.com/Download/item/id/733036.html

[VHDL/FPGA/Verilog] add

4位全加器设计，包含半加器构成全加器，由全加器构成4位全加器及其拓展
4bits (2009-03-23, VHDL, 173KB, 下载9次)

http://www.pudn.com/Download/item/id/684792.html

[VHDL/FPGA/Verilog] 用一位全加器组成四位全加器

用一位全加器组成四位全加器. 所用语言是Verilog HDL. 主要用在加法器的设计中。
All-Canadian with a composed four-adder. The language used is the Verilog HDL. In addition main The design. (2006-01-14, Unix_Linux, 3KB, 下载45次)

http://www.pudn.com/Download/item/id/141043.html

[VHDL/FPGA/Verilog] 基于半加器的全加器描述及仿真

vhdl基于半加器的全加器描述及仿真
VHDL-based increases for the entire increase Description and Simulation (2005-01-13, C/C++, 193KB, 下载25次)

http://www.pudn.com/Download/item/id/1105591470901327.html