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[VHDL/FPGA/Verilog] verilog_niuke

牛客网刷题记录,
Niuke.com question brushing record, (2023-08-19, Verilog, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1692452581746852.html

[VHDL/FPGA/Verilog] Keyboard

客制化机械键盘——从0开始全套资料
Customized mechanical keyboard - complete set of information starting from 0 (2022-08-13, C, 48662KB, 下载0次)

http://www.pudn.com/Download/item/id/1660355768103991.html

[VHDL/FPGA/Verilog] 米联客2020版FPGA课程(MIG DDR篇)-K7

米联客2020版FPGA课程(MIG DDR篇)-K7
FPGA course 2020 (MIG DDR) - KINTEX 7 (2020-11-09, Verilog, 3180KB, 下载30次)

http://www.pudn.com/Download/item/id/1604936664539574.html

[VHDL/FPGA/Verilog] 自动升降电梯

设计了一个6层楼的电梯控制器。该控制器可控制电梯完成6层楼的载客服而且遵循方向优先原则,并能响应提前关门延时关门,并具有超载报警和故障报警;同时指示电梯运行情况和电梯内外请求信息。 其中电梯控制方式为: 1.内部请求优先控制方式 2.单向层层停控制方式 3.方向优先控制方式
A six floor elevator controller is designed. The controller can control the elevator to finish the customer service of six floors and follow the principle of direction priority. It can respond to the door closing delay in advance, and has overload alarm and fault alarm. At the same time, it can indicate the operation of the elevator and the request information inside and outside the elevator. The elevator control mode is: 1. Internal request priority control method 2. One way layer by layer stop control mode 3. direction priority control mode (2020-03-13, VHDL, 931KB, 下载5次)

http://www.pudn.com/Download/item/id/1584091683160018.html

[VHDL/FPGA/Verilog] ZYNQsl

FPGA开发教程,含开发手册和源代码,例程齐全,很好的FPGA学习资料
A tutorial on the development of FPGA, including development manuals and source code, has complete routines and good learning materials for FPGA. (2019-06-12, C/C++, 17223KB, 下载9次)

http://www.pudn.com/Download/item/id/1560301923725413.html

[VHDL/FPGA/Verilog] xapp1052

Xilinx 关于PCIE读写控制的官方例程。
Xilinx PCIE Demo (2016-10-21, VHDL, 13345KB, 下载42次)

http://www.pudn.com/Download/item/id/1476990714874871.html

[VHDL/FPGA/Verilog] Verilog

最经典的VHDL学习资料,千万不要错过哦。夏永闻主编的那本书,不想买书的速来
VHDL learning the most exciting tutorials do not miss it (2016-06-25, VHDL, 22257KB, 下载1次)

http://www.pudn.com/Download/item/id/1466855188304765.html

[VHDL/FPGA/Verilog] beverage

模拟饮料售货机 有限状态机练习的好例子 一厅饮料2.5元 只收1元或5角
A good example of a finite state machine vending machine simulation exercise (2016-05-08, VHDL, 2KB, 下载1次)

http://www.pudn.com/Download/item/id/1462674802170985.html

[VHDL/FPGA/Verilog] OpenM8_CE

大航海脚本美术8脚本,本脚本,已测试只对国服有效
GOV online sc (2016-02-27, C++, 9KB, 下载1次)

http://www.pudn.com/Download/item/id/1456583991841524.html

[VHDL/FPGA/Verilog] MSK

FPGA中实现的MSK调制,带modelsim仿真。实际系统测试通过:载波和调制波信号频率可调。调制框图请参见樊昌信 通信原理247页
MSK modulation implemented in FPGA with modelsim simulation. The actual test system: a carrier wave signal and the modulation frequency is adjustable. See Fan Changxin modulation block diagram of communication theory 247 (2014-04-09, VHDL, 1690KB, 下载69次)

http://www.pudn.com/Download/item/id/2506230.html

[VHDL/FPGA/Verilog] paomadeng

跑马灯代码 阿斯好说的卡上接电话卡结舌杜口京哈蜀客多积货按时间dha空手道会卡水的空间has快结婚ask接电话
good VHDL code asdhkashdkajshdkahskdjhaskjdhkash jkasdhkajsdh akjsdh ajkshd kajshd asjdh kajdh (2011-08-19, VHDL, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/1626525.html

[VHDL/FPGA/Verilog] DMX512_2_23

本系统设计利用FPGA设计了一个接在电脑串口上的一个DMX512协议的转接卡,它可以让你的电脑变成一台超强的电脑灯控制台或者调光台、LED控制器等。通过电脑软件,可以控制电脑灯或者其他DMX512协议的设备,比如LED灯、激光灯、PAR灯、DJ设备等等。 本系统还有体积小巧携带方便等特点,足够一般的娱乐场所、多功能厅、会议厅等场所使用,同时采用电脑进行灯光的控制,也可以提升工程的技术含量,显得更高科技。通过简单更改DMX模块的UART部分,还可以将串口转换usb接口,不过由于手头上的FPGA开发板没有USB接口,所以使用UART接口进行测试。
The system design using FPGA, a serial port on the computer then a DMX512 protocol adapter, it can make your computer into a super computer console or lighting console lights, LED controller. Through computer software, can control lights or other DMX512 protocol computer equipment, such as LED lights, laser lights, PAR lamps, DJ equipment. The system also features compact, portable and so on, is sufficient for most of the entertainment, function rooms, conference rooms and other places to use, while using computer control of lighting can also enhance the project s technical content, appears to higher technology. DMX module by simply changing the UART portion can also convert usb serial interface, however, because the FPGA development board on hand no USB interface, so tests using the UART interface. (2010-07-11, VHDL, 2171KB, 下载270次)

http://www.pudn.com/Download/item/id/1238308.html

[VHDL/FPGA/Verilog] VHDL-dianti

高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。 ): 1统控制的电梯往返于1-9层楼。 2客要去的楼层数可手动输入并显示(设为A数)。 3梯运行的楼层数可自动显示(设为B数)。 4A>B时,系统能输出使三相电机正转的时序信号,使电梯上升; 当A<B时,系统能输出使三相电机反转的时序信号,使电梯下降; 当A=B时,系统能输出使三相电机停机的信号,使电梯停止运行并开门; 5是上升还是下降各层电梯门外应有指示,各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。 注:此为word文档,但里面有源代码。
High-rise elevator control system (Windows platform programming software running on the ispLEVER. ): An elevator control system and from 1-9 floors. 2, the number of passengers going to the floor can manually enter and display (Make A number). 3 ladder run automatically display the number of floors (Set B number). 4A> B, the system can output three-phase motor is transferred to the timing signal to lift up When A <B, the system can output three-phase motor to reverse the timing signal to the lift down When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door 5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch. Note: This is a word document, but inside the source code. (2010-06-10, VHDL, 34KB, 下载19次)

http://www.pudn.com/Download/item/id/1209148.html

[VHDL/FPGA/Verilog] div(FLP)

是Nios II處理器下客製化指令的一個32位元浮點數除法器,可將兩IEEE 754格式的值進行相除
Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division (2009-03-17, VHDL, 18KB, 下载45次)

http://www.pudn.com/Download/item/id/677051.html

[VHDL/FPGA/Verilog] DE2_LCM_CCD_onchip.7z

將DE2連接到LCD版面上 內為友晶客科技公司所附製的程式碼
DE2 will connect to the LCD layout for Terasic off technology companies attached to the system code (2008-10-17, VHDL, 659KB, 下载50次)

http://www.pudn.com/Download/item/id/562751.html

[VHDL/FPGA/Verilog] 899207KEYBOARD_DEC-vhdl

数字平律己的设计非常实用 黄永显示早设计大方ijasd
The design of digital self-Ping Wong Wing-show as early as practical design Dafang ijasd (2008-10-04, VHDL, 1KB, 下载4次)

http://www.pudn.com/Download/item/id/555461.html

[VHDL/FPGA/Verilog] S6_VGA_change

verilog源代码,quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行,
Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off, (2007-09-09, Others, 2512KB, 下载177次)

http://www.pudn.com/Download/item/id/330550.html
总计:17