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按分类查找： VHDL/FPGA/Verilog(109) 其他(30) 嵌入式/单片机/硬件编程(9) 源码/资料(6) 单片机开发(6) Windows编程(3) 通讯编程(3) 其他嵌入式/单片机内容(3) 文章/文档(2) 汇编语言(2) 硬件设计(2) 驱动编程(1) 图形图象(1) 数值算法/人工智能(1) 图形图像处理(1) 串口编程(1) 中间件编程(1) DSP编程(1)

按平台查找： All Quartus II(182)

[源码/资料] 计数器及其动态显示电路的设计

基于Quartus的计数器及其动态显示电路的设计 (2023-01-29, Quartus II, 230KB, 下载0次)

http://www.pudn.com/Download/item/id/1674952620294500.html

[源码/资料] 基于VHDL的简易计时器的设计与实现

本设计简易电子计时器能顺序计时和倒计时，数据范围为1天，即00:00:00 - 23:59:59，同时具有时间设置功能，能从外部设置当前的小时数、分钟数和秒数。本设计使用VHDL语言开发，开发与仿真 IDE 为Quartus II 9.0，在DE2-115开发板上测试运行 (2022-12-08, Quartus II, 1348KB, 下载1次)

http://www.pudn.com/Download/item/id/1670505240609294.html

[驱动编程] 计组计数器设计

能够完成计组计数器的操作，很好很好很好很好 (2022-11-10, Quartus II, 352KB, 下载0次)

http://www.pudn.com/Download/item/id/1668075000348184.html

[源码/资料] verilog 计数器正点原子FPGA开发板测试

verilog 计数器正点原子FPGA开发板测试通过数码管显示输入个数.下载就能显示！可以练习计数(应用,车速检测,脉冲个数记数:流量，脉冲测距等) (2022-07-01, Quartus II, 17222KB, 下载0次)

http://www.pudn.com/Download/item/id/1656642540597357.html

[源码/资料] 一个简单的10进制计数器

一个简单的10进制计数器一个简单的10进制计数器一个简单的10进制计数器 (2022-06-02, Quartus II, 62KB, 下载0次)

http://www.pudn.com/Download/item/id/1654155900272924.html

[源码/资料] 一个简单的分频器

一个简单的分频器,一个简单的分频器,一个简单的分频器 (2022-06-02, Quartus II, 3363KB, 下载0次)

http://www.pudn.com/Download/item/id/1654155780958412.html

[源码/资料] 一个sobel边缘检测器

一个sobel边缘检测器,较为详细，算法实现 (2022-06-02, Quartus II, 58KB, 下载0次)

http://www.pudn.com/Download/item/id/1654155720508130.html

[汇编语言] Verilog

题目2：设计一个表决器要求：实现参数化表决功能，可配置为 3、 5、 7， 2K+1 人（人数<16）表决功能，多数人表决通过则通过；
题目2：设计一个表决器要求：实现参数化表决功能，可配置为 3、 5、 7， 2K+1 人（人数<16）表决功能，多数人表决通过则通过； (2022-05-05, Quartus II, 304KB, 下载0次)

http://www.pudn.com/Download/item/id/1651759140794869.html

[Windows编程] Timer

基于Verilog的timer计时器，start开始，到达设置计时点时输出一个高电平up信号
Timer timer based on Verilog, start, output a high-level up signal when it reaches the set time point (2021-04-21, Quartus II, 7883KB, 下载0次)

http://www.pudn.com/Download/item/id/1618992469896152.html

[VHDL/FPGA/Verilog] FIFO IP核学习与实践

与ROM或RAM的按地址读写方式不同，FIFO的读写遵循“先进先出”的原则，即数据按顺序写入FIFO，先被写入的数据同样在读取的时候先被读出，所以FIFO存储器没有地址线。FIFO有一个写端口和一个读端口外部无需使用者控制地址，使用方便。
Different from ROM or RAM read and write by address, FIFO read and write follow the principle of "first in first out", that is, the data is written into FIFO in order, and the data written first is read out at the same time, so FIFO memory has no address line. FIFO has a write port and a read port, so it is easy to use. (2021-04-20, Quartus II, 1055KB, 下载2次)

http://www.pudn.com/Download/item/id/1618882273767801.html

[其他] 工程文件

FIFO（First?In?First?Out，即先入先出），是一种数据缓冲器，用来实现数据先入先出的读写方式。
FIFO (first in first out) is a data buffer, which is used to read and write data first in first out. (2021-04-20, Quartus II, 6140KB, 下载0次)

http://www.pudn.com/Download/item/id/1618882192980589.html

[VHDL/FPGA/Verilog] rs232 word文档+实验工程

通用异步收发传输器，英文全称Universal asynchronous Receiver/Transmitter，简称UART。 UART是一种通用的数据通信协议，也是异步串行通信口总称，他在发送数据时将并行数据转化为串行数据来传输，在接收数据时将收到的串行数据转化为并行数据来传输。包括RS232、RS499、RS423、RS422、和RS485等接口标准规范和总线规范。
Universal asynchronous receiver (UART) / Transmitter, UART for short. UART is a general data communication protocol, and it is also the general name of asynchronous serial communication port. It transforms parallel data into serial data for transmission when sending data, and converts received serial data into parallel data for transmission when receiving data. Including RS232, rs499, rs423, RS422, RS485 and other interface standards and bus specifications. (2021-04-20, Quartus II, 6962KB, 下载0次)

http://www.pudn.com/Download/item/id/1618881562593282.html

[VHDL/FPGA/Verilog] dds_src

基于FPGA的dds信号发生器，已有仿真tb文件，可发生正弦信号，余弦信号,平台quartus 2
DDS signal generator based on FPGA, has simulation TB file, can generate sine signal, cosine signal (2021-04-18, Quartus II, 25KB, 下载2次)

http://www.pudn.com/Download/item/id/1618732136225214.html

[VHDL/FPGA/Verilog] full adder

vhdl实现全加器，vhdl入门学习，vhdl简单程序
Implementation of full adder with VHDL (2021-04-08, Quartus II, 2740KB, 下载0次)

http://www.pudn.com/Download/item/id/1617863946927858.html

[VHDL/FPGA/Verilog] FREQC

数字频率计的FPGA实现，包括计数器分频器锁存器
Digital frequency meter (2021-04-07, Quartus II, 956KB, 下载0次)

http://www.pudn.com/Download/item/id/1617770658993989.html

[其他] 11_vga_colorbar

显示器 vga彩条显示 verilog代码实现
Display VGA color bar (2021-04-01, Quartus II, 7365KB, 下载0次)

http://www.pudn.com/Download/item/id/1617279106498714.html

[VHDL/FPGA/Verilog] final

使用Verilog写的64阶滤波器，并且设定了定点小数。滤波器的结构是直接型滤波器，没有做任何的优化，但是功能很基本，供大家参考。该工程需要在QuartusII下打开，并且可以直接仿真。
Use Verilog to write the 64 order filter, and set the fixed-point decimal. The structure of the filter is a direct filter, without any optimization, but the function is very basic, for your reference. The project needs to be opened under QuartusII and can be simulated directly. (2021-03-15, Quartus II, 128KB, 下载0次)

http://www.pudn.com/Download/item/id/1615803222550415.html

[VHDL/FPGA/Verilog] key_count

用矩阵键盘实现简易计算器功能支持连续运算
dadafjfakffjalhfoiefgjaf (2021-01-22, Quartus II, 5654KB, 下载0次)

http://www.pudn.com/Download/item/id/1611309935737484.html

[VHDL/FPGA/Verilog] 拔河游戏机

（1）拔河游戏机需要9个发光二极管排成一行，开机后只有中间一个亮点，作为拔河的中间线。游戏双方各持一个按键，迅速且不断地按动产生脉冲，哪方按得快，亮点就向哪方移动，每按一次，亮点移动一次。移到任一方二极管的终端，该方就获胜。此时双方按键均无作用，输出保持，只有经复位后才能使亮点恢复到中心线。（2）显示器显示胜者胜利的次数，裁判按键可以控制开始和清零。
Tug of war game requires 9 light-emitting diodes in a row to turn on. After that, there is only one bright spot in the middle, which serves as the middle line of tug of war. (2021-01-14, Quartus II, 4031KB, 下载1次)

http://www.pudn.com/Download/item/id/1610614505837865.html

[VHDL/FPGA/Verilog] CNT10

基于Quartus II的十进制计数器的实现
Implementation of decimal counter based on Quartus II (2020-12-28, Quartus II, 1431KB, 下载0次)

http://www.pudn.com/Download/item/id/1609140829953288.html

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