DDS波形发生器下载搜索联合开发网

[VHDL/FPGA/Verilog] TS5668N20

多摩川编码器协议详解。目前已验证适用松下A5
the specification of tamagawa fa-coder (2016-08-29, C++ Builder, 1519KB, 下载81次)

http://www.pudn.com/Download/item/id/1472439613538002.html

[VHDL/FPGA/Verilog] FIR

了解FIR滤波器的工作原理，并通过编程学会怎么运用FIR滤波器。
Learn how the FIR filter, and how to learn programming through the use of FIR filters (2016-03-15, C++ Builder, 320KB, 下载2次)

http://www.pudn.com/Download/item/id/1458007770536863.html

[VHDL/FPGA/Verilog] IMbotMod_V4.1

imbot v4.1 DDS ATTACKER
imbot v4.1 DDS ATTACKER (2014-12-04, C++ Builder, 78KB, 下载2次)

http://www.pudn.com/Download/item/id/2667348.html

[VHDL/FPGA/Verilog] DDS

基于dds模块的详细应用,基本了解并熟悉掌握它的应用
on the base of dds s application (2014-08-01, C++ Builder, 492KB, 下载1次)

http://www.pudn.com/Download/item/id/2597831.html

[VHDL/FPGA/Verilog] Fir

FIR滤波器滤波因子的获取及设计，应用例子，源码。
FIR滤波器滤波因子的获取及设计，应用例子，源码。 (2014-01-06, C++ Builder, 292KB, 下载4次)

http://www.pudn.com/Download/item/id/2444243.html

[VHDL/FPGA/Verilog] AD9850

DDS信号模块资料和代码。DDS信号模块资料和代码。
DDS signal module data and code. DDS signal module data and code. (2013-07-06, C++ Builder, 6168KB, 下载8次)

http://www.pudn.com/Download/item/id/2298025.html

[VHDL/FPGA/Verilog] edifier_est101cn

漫步者音箱煲箱软件，有粉红噪音，和信号发生器。Rambler speakers in clay pot box software, pink noise, and the signal generator
漫步者音箱煲箱软件，有粉红噪音，和信号发生器。Rambler speakers in clay pot box software, pink noise, and the signal generator (2013-03-23, C++ Builder, 442KB, 下载3次)

http://www.pudn.com/Download/item/id/2170746.html

[VHDL/FPGA/Verilog] Backoff-verilog

一个简单的总线轮询仲裁器Verilog代码
A simple bus polling arbiter Verilog code (2012-12-04, C++ Builder, 4KB, 下载40次)

http://www.pudn.com/Download/item/id/2071255.html

[VHDL/FPGA/Verilog] PWMPECT

一个飞思卡尔的PWM波形学习资料，还有ect模块的学习。
The PWM waveform a Freescale learning materials, as well as the ect module of learning. (2012-09-20, C++ Builder, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/1998186.html

[VHDL/FPGA/Verilog] Foreign-language-translation

本系统由霍尔传感器、RC滤波电路、单片机AT89S51、系统化LED显示模块、数据存储电路和键盘控制组成。其中霍尔传感器包含信号放大和波形整形。对待测信号进行放大的目的是降低对待测信号的幅度要求；波形变换和波形整形电路则用来将放大的信号转换成可与单片机相连的TTL信号；通过单片机的设置可使内部定时器T1对脉冲输入引脚T0进行控制，这样能精确地算出加到T0引脚的单位时间内检测到的脉冲数；设计中速度显示采用LED模块，通过速度换算得来的里程数采用I2C总线并通过E2PROM来存储，既节省了所需单片机的口线和外围器件，同时也简化了显示部分的软件编程
The design of the bicycle odometer (2012-05-31, C++ Builder, 13KB, 下载4次)

http://www.pudn.com/Download/item/id/1896714.html

[VHDL/FPGA/Verilog] The-design-of-the-bicycle-odometer

本系统由霍尔传感器、RC滤波电路、单片机AT89S51、系统化LED显示模块、数据存储电路和键盘控制组成。其中霍尔传感器包含信号放大和波形整形。对待测信号进行放大的目的是降低对待测信号的幅度要求；波形变换和波形整形电路则用来将放大的信号转换成可与单片机相连的TTL信号；通过单片机的设置可使内部定时器T1对脉冲输入引脚T0进行控制，这样能精确地算出加到T0引脚的单位时间内检测到的脉冲数；设计中速度显示采用LED模块，通过速度换算得来的里程数采用I2C总线并通过E2PROM来存储，既节省了所需单片机的口线和外围器件，同时也简化了显示部分的软件编程
The design of the bicycle odometer (2012-05-31, C++ Builder, 206KB, 下载8次)

http://www.pudn.com/Download/item/id/1896697.html

[VHDL/FPGA/Verilog] counter-interrupt-8-timer-04s

单片机源程序（keilC语言）---计数器中断8次定时04s件，不需编程，但仅是对霍尔传感器测速应用的验证。
SCM source (keilC language)--- counter interrupt 8 timer 04s (2012-05-31, C++ Builder, 8KB, 下载7次)

http://www.pudn.com/Download/item/id/1896665.html

[VHDL/FPGA/Verilog] Uart_2

ＳＴＣ单片机的串口模块可以采用Ｔ１定时器作为它的波特率发生器，同时其内部也集成了一个独立波特率发生器作为串口的波特率发生器，本例子采用的是常用的独立波特率发生器ＢＲＴ作为它的波特率发生器
STC microcontroller serial port T1 timer module can be used as its baud rate generator, while its interior also incorporates an independent Baud Rate Generator as the baud rate generator, is used in this example uses a separate wave BRT as its baud rate generator baud rate generator (2011-09-11, C++ Builder, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/1643819.html

[VHDL/FPGA/Verilog] UART_1

ＳＴＣ单片机的串口模块可以采用Ｔ１定时器作为它的波特率发生器，同时其内部也集成了一个独立波特率发生器作为串口的波特率发生器，本例子采用的是常用的Ｔ１定时器作为它的波特率发生器
STC microcontroller serial port T1 timer module can be used as its baud rate generator, while its interior also incorporates an independent Baud Rate Generator as the baud rate generator, is used in this example uses the T1 timer device as its baud rate generator (2011-09-11, C++ Builder, 1KB, 下载7次)

http://www.pudn.com/Download/item/id/1643817.html

[VHDL/FPGA/Verilog] s

这是运用的MSP430和FPGA所设计的函数信号发生器
This is the use of the MSP430 and the FPGA design function signal generator (2011-08-27, C++ Builder, 5259KB, 下载2次)

http://www.pudn.com/Download/item/id/1632203.html

[VHDL/FPGA/Verilog] Softwave-PWM

软件实现PWM波形，来点亮led灯，使其由明变暗，由暗变明。
PWM waveforms with software (2011-08-02, C++ Builder, 25KB, 下载6次)

http://www.pudn.com/Download/item/id/1612912.html

[VHDL/FPGA/Verilog] FPGAystem

基于FPGA和ARM的数字存储示波器控制系统的设计FPGA and ARM-based digital storage oscilloscope Control System
FPGA and ARM-based digital storage oscilloscope Control System (2011-01-19, C++ Builder, 504KB, 下载11次)

http://www.pudn.com/Download/item/id/1416159.html

[VHDL/FPGA/Verilog] DDSTHEORY

详细介绍了DDS原理，文档容易理解，是硬件开发者不错的选择....
Details of the DDS principle, the document easy to understand, is a good choice for hardware developers .... (2010-01-28, C++ Builder, 444KB, 下载12次)

http://www.pudn.com/Download/item/id/1053330.html

[VHDL/FPGA/Verilog] mimasuo

用数字逻辑实现密码锁的问题，并通过vhdl输出波形。
The realization of digital logic with locks, and through the VHDL output waveform. (2008-12-27, C++ Builder, 90KB, 下载1次)

http://www.pudn.com/Download/item/id/617287.html

[VHDL/FPGA/Verilog] ad9851-1

经典的dds发生器ad9851vhdl的并行通信代码，能实现6倍频和正弦波的输出。不好k我。
Dds generator ad9851vhdl classic parallel communication code, to achieve and 6 octave sine wave output. K my bad. (2007-08-23, C++ Builder, 577KB, 下载138次)

http://www.pudn.com/Download/item/id/322757.html