DDS波形发生器下载搜索联合开发网

[VHDL/FPGA/Verilog] Timer-experiment-inquiry-method

基本部分：用CPU内部定时器查询方式计时,实现每一秒钟输出状态发生一次反转.
Basic part: With the CPU internal timer query mode, the output per second to achieve a reversal of the state. (2015-07-03, Asm, 10KB, 下载1次)

http://www.pudn.com/Download/item/id/1435936377932592.html

[VHDL/FPGA/Verilog] fir16

实现16位fir滤波器计算，利用汇编语言，计算速度快，兼容C2000处理器
16 bit fir calc, used asm , for ti c2000 processer (2015-04-09, Asm, 2KB, 下载2次)

http://www.pudn.com/Download/item/id/1428583407384620.html

[VHDL/FPGA/Verilog] cpu

用CPU内部定时器方式计时，实现每秒钟输出状态发生一次翻转。
CPU internal timer mode with timing to achieve the output state occurs once every second flip. (2014-04-07, Asm, 14KB, 下载2次)

http://www.pudn.com/Download/item/id/2504136.html

[VHDL/FPGA/Verilog] jingsaiqiangda

最新竞赛抢答器，适合初学者使用，实现10秒倒计时功能
Last race Responder, suitable for beginners to use, to achieve 10 seconds countdown function (2013-10-15, Asm, 2KB, 下载1次)

http://www.pudn.com/Download/item/id/2374788.html

[VHDL/FPGA/Verilog] A-FAST-TUNING-16F877-DDS-CONTROLLER

A FAST TUNING 16F877 DDS CONTROLLER
A FAST TUNING 16F877 DDS CONTROLLER (2013-06-13, Asm, 359KB, 下载4次)

http://www.pudn.com/Download/item/id/2277550.html

[VHDL/FPGA/Verilog] chufaasm

除法子程序,R2R3R4R5/R6R7= R4R5,用寄存器区3,返回时为寄存器区3。首先判断商是否溢出。
Division subroutine, R2R3R4R5/R6R7 = R4R5, register area 3, returns to register area 3. First judgment business Whether overflow. (2012-12-18, Asm, 1KB, 下载4次)

http://www.pudn.com/Download/item/id/2087695.html

[VHDL/FPGA/Verilog] 0832

1）了解数模转换的原理及与8086的接口逻辑。 2）掌握使用DAC0832进行数模转换的技术。 1)设计DAC0832与8086CPU的硬件连接图，分配DAC0832的基地址为0FF00H。 2)设计DAC0832的硬件连接，编写程序，实现让0832依次输出方波、负向锯齿波、三角波、正弦波、，并不断重复。要求在示波器上可看到每个波形2个完整的波形。
1) understand the digital-to-analog conversion principle and with the 8086 interface logic. 2) master DAC0832 digital-to-analog conversion technology. 1) design DAC0832 8086CPU hardware connection diagram, distribution the the DAC0832 base address 0FF00H is. 2) design DAC0832 hardware connection, programming 0832 turn output square wave, negative sawtooth, triangle wave, sine wave, and repeated. Requirements each waveform can see two complete waveform on the oscilloscope. (2012-11-17, Asm, 52KB, 下载13次)

http://www.pudn.com/Download/item/id/2050505.html

[VHDL/FPGA/Verilog] qiangdaqi

4路抢答器，一共分为三个模块，包含计时，计分，抢答的功能，
4-way Responder, including timing, scoring function (2012-11-06, Asm, 46KB, 下载6次)

http://www.pudn.com/Download/item/id/2038334.html

[VHDL/FPGA/Verilog] Low-pass-filter-design

低通滤波器设计，主要介绍了低通滤波器设计步骤和方法
Low pass filter design (2012-07-04, Asm, 713KB, 下载8次)

http://www.pudn.com/Download/item/id/1930320.html

[VHDL/FPGA/Verilog] SIM

DAC0832波形发生，三角波，梯形波，方波
DAC0832 waveform, triangular wave, trapezoidal wave, square wave (2012-06-27, Asm, 2KB, 下载5次)

http://www.pudn.com/Download/item/id/1924185.html

[VHDL/FPGA/Verilog] 8253

基于MASM的实验二8253定时器计数器实验设计！
Based on the experiment MASM two 8253 timer counter experiment design! (2012-03-29, Asm, 9KB, 下载17次)

http://www.pudn.com/Download/item/id/1810540.html

[VHDL/FPGA/Verilog] expt12_10_phas

基于fpga和sopc的用VHDL语言编写的EDA数字移相信号发生器
FPGA and SOPC based on the use of VHDL language shift EDA Digital Signal Generator (2007-11-13, Asm, 45KB, 下载12次)

http://www.pudn.com/Download/item/id/359502.html

[VHDL/FPGA/Verilog] expt12_9_dds

基于fpga和sopc的用VHDL语言编写的EDA的DDS信号发生器
FPGA and SOPC based on the use of VHDL language EDA s DDS Signal Generator (2007-11-13, Asm, 39KB, 下载16次)

http://www.pudn.com/Download/item/id/359501.html

[VHDL/FPGA/Verilog] expt81_schk

基于fpga和sopc的用VHDL语言编写的EDA序列检测器
FPGA and SOPC based on the use of VHDL language EDA sequence detector (2007-11-13, Asm, 10KB, 下载6次)

http://www.pudn.com/Download/item/id/359488.html

[VHDL/FPGA/Verilog] expt71_singt

基于fpga和sopc的用VHDL语言编写的EDA正弦信号发生器
FPGA and SOPC based on the use of VHDL language EDA sinusoidal signal generator (2007-11-13, Asm, 36KB, 下载12次)

http://www.pudn.com/Download/item/id/359485.html

[VHDL/FPGA/Verilog] szxhfsq

数字信号发生器可以用来解决数字信号，我说的不好，请大家自己
Digital signal generator can be used to solve the digital signal, I say bad, please everyone their own (2007-08-09, Asm, 75KB, 下载9次)

http://www.pudn.com/Download/item/id/317496.html

[VHDL/FPGA/Verilog] fipppr

FIR滤波器包括所有的源程序
FIR filter all of the source. (2007-05-29, Asm, 5KB, 下载27次)

http://www.pudn.com/Download/item/id/289820.html

[VHDL/FPGA/Verilog] day2006-3-3

空调控制器，用6502系列CPU作为主芯片，控制继电器，实现空调的加热，致冷，通风，定时等设置。
HVAC, and 6502 series CPU chip as the main control relays, Implementation of the air conditioning heating, cooling, ventilation, such as setting up regularly. (2007-05-19, Asm, 90KB, 下载43次)

http://www.pudn.com/Download/item/id/284447.html

[VHDL/FPGA/Verilog] firnew

数字滤波的设计:FIR滤波器,设计滤波器采样频率为600hz，截止频率200hz的高通滤波器
Digital Filter Design : FIR filter, the sampling frequency filter design to 600hz, 200hz cutoff frequency of the high pass filter (2006-03-16, Asm, 2KB, 下载47次)

http://www.pudn.com/Download/item/id/154898.html

[VHDL/FPGA/Verilog] Digital_030423

服务器的的板在载控制器的AHDL程序,包括原理图编译,用在EPM7128上(CPLD).
server board controller is contained in the AHDL procedures, including schematic compiler, the use EPM7128 (CPLD). (2005-12-10, Asm, 514KB, 下载8次)

http://www.pudn.com/Download/item/id/132046.html