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[VHDL/FPGA/Verilog] lvboqiquzaosheng

滤波器去除噪声以及加随机噪声，显示图形fir滤波器
Filter to remove the noise and random noise, graphic display (2015-05-05, Flex, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/1430812302724934.html

[VHDL/FPGA/Verilog] 2

8位计数器，可逆，可加可减，可以以时钟输入也可手动输入
8-bit counter, reversible, can be increased or decreased, can be input clock can also manually enter (2007-11-02, Flex, 192KB, 下载1次)

http://www.pudn.com/Download/item/id/354493.html

总计:2