用VHDL语言设计并实现一电路，其功能是8个数码管分别显示数字0－7。首先是数码管0显示0，其他数码管不显示；然后是数码管1显示1，其他数码管不显示；依此类推，数码管7显示完后再显示数码管0，这样循环下去。（提示：数字0－7的循环可以使用8进制计数器对1Hz的时钟信号进行计数得到，计数器的输出送到BCD到七段数码管的译码器，由其驱动数码管显示相应的数字。）
Using VHDL language to design and implement a circuit, its function is 8 digital display digital 0-7. The first is the digital tube 0 display 0, other digital tube does not show; then digital tube 1 display 1, other digital tube does not show; and so on, digital tube 7 display after the display digital tube 0, so cycle. (hint: 0-7 cycles can be used 8 binary counter clock signal of the 1Hz count, the counter output to BCD to seven digital tube decoder, driven by digital display the corresponding number.) (2017-11-09, Proteus, 108KB, 下载6次)
Verilog HDL实现十进制计数器,FPGA ISE开发环境
Verilog HDL decimal counter (2017-05-24, Proteus, 1302KB, 下载2次)