添加了额外的信号来控制来自用户端的序列，并具有加载功能。请首先参考可编程序列检测器。
Added extra signal to control sequence from user end with load functionality. Please refer Programmable Sequence Detector first. (2024-03-29, Verilog, 0KB, 下载0次)
数据流多路复用器，，
DataStreamMultiplexer,, (2023-08-25, Verilog, 0KB, 下载0次)
通用移位寄存器，该项目概述了使用OpenLane和Skywater130 PDK的通用移位寄存器的RTL到GDSII。OpenLane我...
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow. (2022-07-19, Verilog, 104KB, 下载0次)
EDAC_SDRAM_Controller，使用EDAC SDRAM控制器缓解COTS SDRAM中的单事件上升
EDAC_SDRAM_Controller,Mitigating Single-Event Upsets in COTS SDRAM using an EDAC SDRAM Controller (2017-10-30, Verilog, 130783KB, 下载0次)
vsdmixedsignalflow，该项目描述了模拟IP，2:1模拟多路复用器的PNR是如何通过开源EDA工具进行的，Op...
This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also discusses the steps to modify the current IP layouts inorder to ensure its acceptance by the EDA tools. (2020-12-06, Verilog, 4685KB, 下载0次)
开放寄存器设计工具，使用SystemRDL或JSpec输入生成寄存器RTL、模型和文档的工具
open-register-design-tool,Tool to generate register RTL, models, and docs using SystemRDL or JSpec input (2022-09-04, Verilog, 2515KB, 下载0次)