\--设计概述：用于8位数据和1位奇偶校验的串并转换器\--奇偶校验可以是奇数或偶数\--生成值...，
-- Design Overview: Serial to parallel converter for 8 bit data and one bit parity -- Parity can either be odd or even -- Produces a valid signal as well as a bad_parity, when data is output (2013-02-07, VHDL, 0KB, 下载0次)
动态随机存取存储器
DpRam (2023-06-11, VHDL, 0KB, 下载0次)