[VHDL/FPGA/Verilog] DE2_SDCARD
DE2 开发板上，NIOS编程。对SD卡以及USB的读写操作的实例。我的代码及工程绝对完整！代码其实是Verilog编写的。
DE2 development board, NIOS programming. On the SD card and USB examples of read and write operations. My absolute integrity of code and works! Verilog code is written. (2009-08-16, VHDL, 11572KB, 下载700次)
[VHDL/FPGA/Verilog] ADC
用verilog编程实现的基于FPGA的AD数据采集程序
Verilog Programming with FPGA-based data collection procedures AD (2008-06-14, VHDL, 488KB, 下载651次)
[图形图像处理] video_process_base_on_DSPandFPGA
基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型
化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了
三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.
Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic, (2009-01-23, VHDL, 534KB, 下载593次)
[其他书籍] 61EDA_B79
书名：LDPC原理与应用。是国内第一本介绍用LDPC编、译码基本原理及应用技术的一本书。对用 vhdl 或verilog实现硬件编程LDPC的人开发无线通信是很好的资料
Title: LDPC Principles and Applications. Is the first book describes using LDPC Encoding and Decoding the basic principles and application of technology, a book. Right to use vhdl or verilog hardware programming LDPC people to achieve development of wireless communications is a very good information (2009-10-30, VHDL, 8217KB, 下载475次)
[VHDL/FPGA/Verilog] sram
FPGA向SRAM中写入数据(VHDL编程)，包含通用fifo，sram等
FPGA to the SRAM write data (VHDL programming), contains general fifo, sram, etc. (2008-06-28, VHDL, 264KB, 下载464次)
[VHDL/FPGA/Verilog] pingpang
关于乒乓操作的，对于数据缓存有很大的用处
On the ping-pong operation of data cache for the great usefulness of (2009-05-15, VHDL, 163KB, 下载423次)
[VHDL/FPGA/Verilog] FPGA_image
fpga实现图像处理，JPEG标准下图象压缩，VHDL语言编程。
fpga implementation image processing, JPEG image compression under the standard, VHDL language programming. (2009-10-22, VHDL, 289KB, 下载389次)
[VHDL/FPGA/Verilog] alu
设计带进位算术逻辑运算单元，根据74LS181功能表，用Verilog HDL硬件描述语言编程实现ALU181的算术逻辑运算功能，编辑实验原理图，在算术逻辑单元原理图上，将其扩展为带进位的算术逻辑运算单元，对其进行编译，并设计波形对其进行仿真验证，最后下载验证
Design into the digital arithmetic logic operation unit, in accordance with menu 74LS181 with Verilog HDL hardware description language programming ALU181 function arithmetic logic operations, editing Experimental schematic diagram, in the Arithmetic Logic Unit schematic diagram on its expansion into the spaces for arithmetic logic operation unit, its compiler, and the design of their simulation waveforms, and finally download the verification (2009-04-26, VHDL, 652KB, 下载370次)
[VHDL/FPGA/Verilog] AHB
用VHDL编写的AMBA总线的AHB代码
Written with the VHDL code for AMBA bus AHB (2010-03-14, VHDL, 194KB, 下载361次)
[VHDL/FPGA/Verilog] FPGA
FPGA应用开发入门与典型实例 代码
FPGA（现场可编程逻辑器件）以其体积小、功耗低、稳定性高等优点被广泛应用于各类电子产品的设计中。本书全面讲解了FPGA系统设计的背景知识、硬件电路设计，硬件描述语言Verilog HDL的基本语法和常用语句，FPGA的开发工具软件的使用，基于FPGA的软核嵌入式系统，FPGA设计的基本原则、技巧、IP核， FPGA在接口设计领域的典型应用，FPGA＋DSP的系统设计与调试，以及数字变焦系统和PCI数据采集系统这两个完整的系统设计案例。
FPGA Application Development and Typical examples of code for FPGA (field programmable logic device) for its small size, low power consumption, high stability, the advantages are widely used in the design of electronic products. This book comprehensively explained the background FPGA system design, hardware design, hardware description language Verilog HDL syntax and basic common statement, FPGA use of the software development tools, FPGA-based soft-core embedded systems, FPGA design of the basic principles , skills, IP core, FPGA interface design field in a typical application, FPGA+ DSP system design and debug, and digital zoom systems and PCI data acquisition system design of two cases of complete system. (2010-04-30, VHDL, 10723KB, 下载316次)
[VHDL/FPGA/Verilog] CyclonePLL
Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。
PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟到输出（TCO）和建立（TSU）时间。
Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle and the external clock output for system-level clock management and offset control. Altera ® Quartus ® II software does not require any external devices, you can enable the Cyclone PLL and related functions. This article describes how to design and use the Cyclone PLL features. PLL clock devices commonly used in the synchronization of internal and external clock, so that the inner workings of the clock frequency higher than the external clock, clock delay and clock skew minimum, reduce or adjust the clock to the output (TCO) and the establishment of (TSU) time. (2010-01-07, VHDL, 541KB, 下载311次)
[VHDL/FPGA/Verilog] fir_lms
基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。
FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter. (2009-04-27, VHDL, 12KB, 下载305次)
[VHDL/FPGA/Verilog] DDSSYNCtrl_tri_face
AD9910的实验代码，使用并口实现快速调频，编程通过原理图和语言混合
AD9910 experimental code, the use of parallel fast FM, the programming language through the schematic and mixed (2010-11-08, VHDL, 16593KB, 下载297次)
[VHDL/FPGA/Verilog] AD7656
AD7656转换芯片的VHDL语言驱动程序，实现8路同时采样并行输出16位数据，并附有仿真波形，需要的就下载吧
VHDL language conversion chip AD7656 driver, to achieve 8 simultaneously sampled 16-bit parallel output data, together with simulation waveforms (2010-09-29, VHDL, 303KB, 下载287次)
[VHDL/FPGA/Verilog] DDs
这是我的毕业设计，是用VHDL编程的直接扩频发生器。
This is my graduation project is the use of VHDL programming direct spread-spectrum generator. (2008-04-15, VHDL, 449KB, 下载286次)
[VHDL/FPGA/Verilog] EDAdeisgn(2)
该文件中是关于一些VHDL许多编程实例以及源码分析，希望对VHDL爱好者有用。卷2实例包括：多路彩灯控制器的设计与分析、智力抢器的设计与分析、微波炉控制器、数据采集控制系统、电梯控制器的设计与分析
The document is on a number of VHDL source code in many programming examples and analysis, in the hope that useful VHDL enthusiasts. Volume 2 Examples include: multi-way lantern controller design and analysis, intelligence steal the design and analysis, microwave oven controller, data acquisition and control systems, elevator controller design and analysis (2008-04-15, VHDL, 4836KB, 下载274次)
[VHDL/FPGA/Verilog] custom_cordic
verilog编程开发的cordic例程，计算SIN,COS功能与计算幅值角度功能可设定，运算宽度可设定，并有完善的TESTBENCH。
Verilog programming developed CORDIC routines to calculate SIN, COS function and calculating the amplitude of the perspective of function can be set, computing the width can be set, and perfect TESTBENCH. (2009-01-15, VHDL, 117KB, 下载252次)
[VHDL/FPGA/Verilog] RS(204_188)decoder
<Verilog HDL 语言编程》
RS(204,188)译码器的设计
<Verilog HDL language programming RS (204,188) Decoder (2008-07-20, VHDL, 11KB, 下载243次)
[VHDL/FPGA/Verilog] whitenoise
信噪比可变的加性高斯白噪声信道下信号发生器的VHDL语言编程实现
the realization of data-creater on AWGN channel (2010-10-14, VHDL, 68KB, 下载235次)
[VHDL/FPGA/Verilog] I2C-Master-_-Slave-Core
用verilog 实现的 iic 总线编程，包括master，和slave的编程，很详细的iic总线编程
Iic-bus implemented using verilog programming, including the master, and slave programming, a very detailed iic-bus programming (2011-03-28, VHDL, 2130KB, 下载219次)