vhdl 编写的cpu 代码, 详细说明了各个部分的功能及所有对应的代码，对cpu架构的学习和vhdl 编程有很大帮助
vhdl code for simple CPU (2017-11-05, VHDL, 977KB, 下载2次)
synplify使用教程，快熟学会synplify的使用，以及基本的编程。
synplify teaching book，let you study synplify quickly。 (2011-04-17, VHDL, 65KB, 下载9次)
CY7C68013A提供的端口FIFO的读写操作，与普通FIFO读写操作方式一样。CY7C68013A为每个端口提供了“空”标志、“满”标志和“ 可编程级”标志。FPGA检测这些信号，用于控制读写的过程
CY7C68013A available port FIFO read and write operations, and general FIFO read and write operations the same way. CY7C68013A for each port provide a " empty" signs, " full" signs and " programmable-class" logo. FPGA detect these signals, used to control the process of reading and writing (2009-11-10, VHDL, 1350KB, 下载121次)
寝室哥们喜欢编程，闲着无聊就帮我做了这个，能用就用。
Bedroom buddies like programming, idle bored helped me to do this, can be used. (2008-06-11, VHDL, 145KB, 下载5次)