本项目的主要目标是使用VHDL编程设计一种组合锁状态机。在本设计中，我们遵循了一些原则...，
The main aim in this project is to design a combination lock state machine design using VHDL programming. In this design we follow some procedure to execute the program like compilation, stimulation and execution of the waveform, which results the combinational lock machine it is also an example of a mealy machine. (2023-10-06, VHDL, 0KB, 下载0次)
使用现场可编程门阵列（FPGA）设计和实现交叉口交通控制系统（交通模块）...，
Designing and implementing a traffic control system for an intersection (Traffic Module) by using a field programmable gate array (FPGA) integrated circuit. (2020-06-23, VHDL, 0KB, 下载0次)
sampleofbus，简单的总线编程，经过仿真，结果正确
sampleofbus, simple programming bus, after simulation, the results of the correct (2009-06-17, VHDL, 266KB, 下载1次)