在本项目中，FPGA被编程为使用VHDL执行一维时域卷积。它由两个主要部分组成，将由......、...，
In this project a FPGA is programmed to perform 1-D time domain convolution using VHDL. It consists of two major parts to be completed which were the DMA interface between memory(DRAM) and the user_app and the design oof the signal and kernel buffers to perform convolution. (2022-02-11, VHDL, 0KB, 下载0次)
ZYNQ 的gpio 可以通过MIO 引出到PS 端的引脚，本例子
的gpio 通过MIO 引出，控制LED 灯D29。
ZYNQ GPIO can be drawn to the PS through the MIO pin, this example GPIO led by MIO, control LED lamp D29. (2017-04-06, VHDL, 4513KB, 下载6次)
可编程逻辑器件对TCD2252的驱动程序VHDL
Programmable logic device drivers for TCD2252 VHDL (2014-03-24, VHDL, 1KB, 下载4次)
TCD1501D驱动程序 对线阵CCD传感器TCD1501驱动编程
The TCD1501D driver linear CCD sensor TCD1501 driver programming (2013-05-16, VHDL, 1KB, 下载18次)