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按分类查找： All 通讯编程(7)

按平台查找： All IDL(7)

[通讯编程] xnqropz

用verilog编写的bch译码器,包括测试文件,随机加载了比特流,进行了测试,
The bch decoder written in verilog, including the test file, loaded the bitstream randomly and tested it. (2018-07-30, IDL, 186KB, 下载0次)

http://www.pudn.com/Download/item/id/1532919586105221.html

[通讯编程] vudeo-bule

Clock signal input that requires a top-level file to produce an address adder with automatic add-on function
Clock signal input that requires a top-level file to produce an address adder with automatic add-on function (2018-07-30, IDL, 542KB, 下载0次)

http://www.pudn.com/Download/item/id/1532918167574748.html

[通讯编程] prunsmity_containment

蓝牙的一个ip RTL 核,不知道对大家有没有用？谢谢, (2018-06-17, IDL, 4KB, 下载0次)

http://www.pudn.com/Download/item/id/1529243562911358.html

[通讯编程] 7640972

这个是UART的控制器,已经跑通过,分4个模块,波特率生成,发送,接收和fifo,可供初学者参考 (2018-06-17, IDL, 3KB, 下载0次)

http://www.pudn.com/Download/item/id/1529243278925517.html

[通讯编程] qqvariants-game

iic总线控制器VHDL实现 -- VHDL Source Files i2c vhd -- top level file i2c_ (2018-06-17, IDL, 834KB, 下载0次)

http://www.pudn.com/Download/item/id/1529237467459450.html

[通讯编程] rplptter

最近在做毕设,ldpc码的编解码实现,这个是verilog实现, (2018-06-12, IDL, 4KB, 下载0次)

http://www.pudn.com/Download/item/id/1528791696151225.html

[通讯编程] nonfigm

这是我做的一个BCH译码模块硬件语言模块,这么好的东西上传上来还不让下载 (2018-04-22, IDL, 4KB, 下载1次)

http://www.pudn.com/Download/item/id/1524365114659018.html

总计:7