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EWR WRWT WQE QWRW ewweeewr (2018-05-03, VHDL, 1KB, 下载1次)
計算八位元有多少個1
module bitcount (Clock, Resetn, LA, s, Data, B, Done)
input Clock, Resetn, LA, s
input [7:0] Data
output [2:0] B
output Done
wire [7:0] A
wire z
reg [1:0] Y, y
reg [2:0] B
reg Done, EA, EB, LB
Calculate the number of eight yuan 1 module bitcount (Clock, Resetn, LA, s, Data, B, Done) input Clock, Resetn, LA, s input [7:0] Data output [2:0] B output Done wire [7:0] A wire z reg [1:0] Y, y reg [2:0] B reg Done, EA, EB, LB (2011-06-26, VHDL, 118KB, 下载2次)
一个比较好的交通灯控制器系统，采用VARILOG HDL语言编程。
A better traffic light controller system that uses VARILOG HDL language programming. (2009-09-26, VHDL, 566KB, 下载5次)
数字系统设计的编程，实现四选一的多路选择器，用ｖｅｒｉｌｏｇ实现。
The design of digital systems programming, to achieve the election of the four MUX, with the realization of verilog. (2009-06-25, VHDL, 49KB, 下载11次)
简述cpu的工作设计的原理，应用硬件编程语言实现系统的设计功能
it will be helpful for you to design a system (2009-05-26, VHDL, 30KB, 下载1次)
基于Q2的VERILOG编程的3-8译码器的源代码，已经经过调试和仿真，适合相关开发人员。
3-8decode (2009-04-28, VHDL, 32KB, 下载1次)
此程序为硬件EDA编程，实现了十位的计数器功能，在平台中可以模块化应用
This procedure EDA hardware programming, implementation of the counter 10 functions in a modular application platform can be (2009-04-05, VHDL, 6KB, 下载2次)
硬件描述语言AHDL设计编程源程序，包括各种不同用途的代码
AHDL hardware description language design programming source code, including a variety of different uses of the code (2009-02-21, VHDL, 483KB, 下载3次)
数字部件设计编程，verylog编程，计算机ALU部件编程
Digital Component Design Programming, verylog programming, computer programming ALU components (2009-02-06, VHDL, 173KB, 下载1次)
通过硬件描述语言编程实现了计数器，可以实现二十四进制的数
Through hardware description language programming to achieve the counter, can achieve a few 24 M (2008-10-10, VHDL, 143KB, 下载2次)
这个压缩程序包含两个60进制计数器的源代码，可供习惯不同编程风格的用户使用
The compression process consists of two 60-band counter source code for different programming style habits of users (2008-05-25, VHDL, 1KB, 下载36次)