实现数字图像的采集，vrilog编程，已经通过验证，可用
Digital image acquisition, vrilog programming has been verified and available (2013-04-02, VHDL, 1KB, 下载3次)
从算法设计到硬件逻辑的实现（夏宇闻）,
可编程逻辑部件的使用和范例
From algorithm design to hardware logic implementation (XIA Yu-Wen), programmable logic components and examples of the use of (2009-11-10, VHDL, 2320KB, 下载3次)
基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型
化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了
三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.
Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic, (2009-01-23, VHDL, 534KB, 下载593次)
现场可编程逻辑门阵列在实时数字图像处理中的应用
Field-programmable gate array logic in real-time digital image processing (2008-05-16, VHDL, 156KB, 下载31次)