Pi5帽子上的AMD Xilinx Artix 50T FPGA，具有PCIe和GPIO互连以及SPI编程
An AMD Xilinx Artix 50T FPGA on a Pi5 Hat with PCIe and GPIO interconnects as well as SPI programming (2024-03-25, Verilog, 0KB, 下载0次)
MIPS-32单周期处理器，具有R型指令。通过Verilog.编程。，
MIPS -32 single cycle processor with R type instruction. Programmed via Verilog., (2019-02-16, Verilog, 0KB, 下载0次)
MipSim是使用Flutter desktop for linux的Mips处理器管道的汇编程序。它是计算机组织的项目（第三计算机工程...，
MipSim is assembler for Mips processor pipeline using Flutter desktop for linux. It s project in computer organization (3rd Computer Engineering). (2019-11-23, Verilog, 0KB, 下载0次)
实现Verilog代码来模拟MIPS处理器，并使用Python GUI汇编程序。，
Implement a Verilog code to simulate the MIPS Processor and using Python GUI assembler., (2017-12-23, Verilog, 0KB, 下载0次)
FPGA(现场可编程门阵列)与 CPLD(复杂可编程逻辑器件)都是可编程逻辑器件，它们是在PAL,GAL等逻辑器件的基础之上发展起来的。同以往的PAL,GAL等相比较，FPGA／CPLD的规模比较大，它可以替代几十甚至几千块通用IC芯片。这样的FPGA／CPLD实际上就是一个子系统部件。
本次EDA课程设计就是利用VerilogHDL来设计设计一个2选1多路选择器
FPGA (field programmable gate array) and CPLD (complex programmable logic device) are programmable logic devices. They are developed on the basis of pal, gal and other logic devices. Compared with pal and gal, FPGA / CPLD has a large scale and can replace dozens or even thousands of general IC chips. Such FPGA / CPLD is actually a subsystem component.
This EDA course design is to use Verilog HDL to design a 2-out-of-1 multiplexer (2020-05-11, Verilog, 1KB, 下载0次)
FPGA(现场可编程门阵列)与 CPLD(复杂可编程逻辑器件)都是可编程逻辑器件，它们是在PAL,GAL等逻辑器件的基础之上发展起来的。同以往的PAL,GAL等相比较，FPGA／CPLD的规模比较大，它可以替代几十甚至几千块通用IC芯片。这样的FPGA／CPLD实际上就是一个子系统部件。
本次EDA课程设计就是利用VerilogHDL来设计设计一个4位加法器
FPGA (field programmable gate array) and CPLD (complex programmable logic device) are programmable logic devices. They are developed on the basis of pal, gal and other logic devices. Compared with pal and gal, FPGA / CPLD has a large scale and can replace dozens or even thousands of general IC chips. Such FPGA / CPLD is actually a subsystem component.
This EDA course design is to use Verilog HDL to design a 4-bit adder (2020-05-11, Verilog, 1KB, 下载0次)
FPGA(现场可编程门阵列)与 CPLD(复杂可编程逻辑器件)都是可编程逻辑器件，它们是在PAL,GAL等逻辑器件的基础之上发展起来的。同以往的PAL,GAL等相比较，FPGA／CPLD的规模比较大，它可以替代几十甚至几千块通用IC芯片。这样的FPGA／CPLD实际上就是一个子系统部件。
本次EDA课程设计就是利用VerilogHDL来设计设计一个自动售货机
FPGA (field programmable gate array) and CPLD (complex programmable logic device) are programmable logic devices. They are developed on the basis of pal, gal and other logic devices. Compared with pal and gal, FPGA / CPLD has a large scale and can replace dozens or even thousands of general IC chips. Such FPGA / CPLD is actually a subsystem component.
This EDA course design is to use Verilog HDL to design a vending machine (2020-05-11, Verilog, 1KB, 下载0次)
引入了Verilog HDL硬件描述语言介绍了信号处理与硬线逻辑设计的关系，以及有关的基本概念。
In this paper, Verilog HDL hardware description language is introduced to introduce the relationship between signal processing and hardware logic design, as well as the related basic concepts. (2019-10-28, Verilog, 1323KB, 下载4次)
EP2S30资料，FPGA编程，适用于EP2S30芯片
EP2S30 datasheet,FPGA programer,adapt for EP2S30 device. (2019-01-02, Verilog, 299KB, 下载0次)
用Verilog编程实现一个4bit加法器
Write a program to implement a 4 bit-adder. (2018-04-11, Verilog, 34KB, 下载1次)
用Verilog语言编程实现4位BCD计数器的功能
Write the programm with Verilog language to implement the function of 4 - bit BCD counter. (2018-04-11, Verilog, 25KB, 下载14次)
利用Verilog语言，在PFGA中实现对16位DA芯片AD5761的输出电压进行或編程设置
Using Verilog language, the output voltage of 16 bit DA chip AD5761 is programmed or programmed in PFGA (2017-10-24, Verilog, 1KB, 下载38次)