verilog，arty z7 10，维瓦多
verilog, arty z7 10 , vivado (2024-02-12, VHDL, 0KB, 下载0次)
半加器、全加器、多路复用器、编码器、解码器、触发器、锁存器、寄存器、FSM和微型计算器项目。，
Half Adder, Full Adder, Multiplexer, Encoder, Decoder, Flip Flop, Latch, Register, FSM and Mini-Calculator project., (2018-07-19, VHDL, 0KB, 下载0次)
用verilog语言编写的全加器模块代码，在ISE软件环境下编译开发，希望对大家有所帮助！
With verilog language full adder module code in ISE software compiler development environment, we want to help! (2016-04-13, VHDL, 151KB, 下载2次)
曼彻斯特总线信号编码解码的VHDL程序应用于通讯技术
Manchester bus encoder and decoder (2015-12-08, VHDL, 197KB, 下载3次)
8位加法器源代码，vivado实现编写。
8 adder Source, vivado achieve write. (2015-12-01, VHDL, 451KB, 下载21次)
基于FPGA的由两个四位全加器合成的八位全加器
Based on the synthesis of two four eight full adder full adder FPGA (2014-03-28, VHDL, 420KB, 下载8次)
基于VHDL语言的HD4069曼彻斯特编码器实现
Based on VHDL HD4069 Manchester encoder implementation (2013-01-29, VHDL, 168KB, 下载15次)
VHDL和verilog语言，在de2板上实现俄罗斯方块 ，VGA显示，改进版
VHDL and verilog language, Tetris, de2 board, VGA display, an improved version of (2012-10-03, VHDL, 15015KB, 下载45次)
8*8的乘法器，其中使用了门电路和全加器来实现的，全加器用以实现进位运算，
8* 8 multiplier, which uses the gate and full adder to implement the full adder to achieve binary operations (2012-07-12, VHDL, 2KB, 下载3次)
8*8点阵实现俄罗斯方块功能，左移右移以及消行
8* 8 dot matrix Tetris (2012-06-12, VHDL, 1076KB, 下载6次)
基于FPGA 的全加器设计。应用软件是Qartaus 2
full_adder design (2012-04-24, VHDL, 250KB, 下载4次)
PS/2键盘加DDS的verilog 设计
PS/2 keyboard plus the verilog design DDS (2011-08-18, VHDL, 1923KB, 下载2次)
LCD1602控制器，液晶显示控制模块。VHDL代码。comment是自己加的
LCD1602 controller (2011-05-23, VHDL, 2KB, 下载4次)
以ISE为平台，用Verilog编写的32位全加器模块，只需在Top模块中调用即可
The ISE as a platform, written with Verilog 32-bit full adder module, simply call the module to Top (2011-05-21, VHDL, 2KB, 下载5次)
lcd12864 全屏显示
汉字加字符
lcd12864 full screen characters plus characters (2010-05-28, VHDL, 1KB, 下载10次)
算数逻辑单元，实现算数加、减，加1、减1运算和逻辑与、或、非和传递
Arithmetic logic unit, to achieve arithmetic add, subtract, plus one, minus one operation and logical AND, OR, and transmission of non- (2009-11-04, VHDL, 296KB, 下载17次)
一个半加器，具有进位和位数相加的基本功能，可作为全加器的基本模块
One and a half adder with binary and the sum of the basic functions of the median, full adder can be used as the basic module (2009-08-11, VHDL, 72KB, 下载2次)
VHDL编写计算器，功能包括：加，减，乘，除。通过keypad输入及输出
Calculator written with VHDL (2009-07-11, VHDL, 307KB, 下载85次)
八位加法器的原理图实现方法和一位半加器 全加器的原理图实现
Eight adder schematic diagram of the method and a half adder full adder schematic diagram of the realization of (2009-06-07, VHDL, 268KB, 下载4次)
一位全加器源码实现了MAX及其一系列器件实现全加的功能
A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian (2009-04-25, VHDL, 13KB, 下载6次)