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[VHDL/FPGA/Verilog] fpga_video

使用MicroBlaze操作HDMI视频。锡林克斯斯巴达6。
Manipulation of HDMI video with MicroBlaze. Xilinx Spartan 6. (2015-05-07, VHDL, 157KB, 下载0次)

http://www.pudn.com/Download/item/id/1430994545923109.html

[VHDL/FPGA/Verilog] Keyboard

客制化机械键盘——从0开始全套资料
Customized mechanical keyboard - complete set of information starting from 0 (2022-08-13, C, 48662KB, 下载0次)

http://www.pudn.com/Download/item/id/1660355768103991.html

[VHDL/FPGA/Verilog] 4位二进制全加器

在两位全加器的基础上，使用元件例化，实现四位二进制数的加法功能。
Using component instance to realize the addition of Four Binary Numbers (2018-12-22, VHDL, 123KB, 下载1次)

http://www.pudn.com/Download/item/id/1545493346668174.html

[VHDL/FPGA/Verilog] 基于VHDL实现单精度浮点数的加-减法运算

vhdl 加法器和减法器希望对VHDL的同学有参考作用
VHDL adder and function as relative reference (2018-08-03, Verilog, 654KB, 下载12次)

http://www.pudn.com/Download/item/id/1533302089316213.html

[VHDL/FPGA/Verilog] Tetris_Zedboard

俄罗斯方块俄罗斯方块”FPGA实现本项目主要在FPGA上实现了一个经典小游戏“俄罗斯方块”。本项目基本解决方案是，使用Xilinx Zynq系列开发板ZedBoard作为平台，实现主控模块，通过VGA接口来控制屏幕进行显示。
New Tetris (2016-06-22, VHDL, 5442KB, 下载10次)

http://www.pudn.com/Download/item/id/1466578059107604.html

[VHDL/FPGA/Verilog] alu1

设计16位算术逻辑单元，能实现加、减、加1、减1、与、或、非、传送的功能。
Design of 16-bit arithmetic logic unit, to add, subtract, add 1, subtract 1, AND, OR, NOT, transfer function. (2013-12-23, VHDL, 381KB, 下载3次)

http://www.pudn.com/Download/item/id/2433532.html

[VHDL/FPGA/Verilog] manchster

曼彻斯特代码程序完整可以直接用将输入数据修改就可以用
Manchester code integrity of the process can be directly used to modify the input data can be used (2013-07-23, VHDL, 1KB, 下载5次)

http://www.pudn.com/Download/item/id/2312248.html

[VHDL/FPGA/Verilog] am

实验一模拟调制解调,调幅波的调制解调，以及加噪滤波
Experiment one analog modulation and demodulation, amplitude modulated wave modulation and demodulation, and adding noise filtering (2013-06-09, matlab, 1KB, 下载9次)

http://www.pudn.com/Download/item/id/2275042.html

[VHDL/FPGA/Verilog] binBCD

bcd码ASIC码的FPGA VHDL实现加仿真
bcd to ASIC in FPGA VHDL (2012-12-29, VHDL, 205KB, 下载2次)

http://www.pudn.com/Download/item/id/2101132.html

[VHDL/FPGA/Verilog] adder16

16位全加器，适合初学者用，上实验课使用杠杠的！！！
The experimental class of 16-bit full adder, suitable for beginners, on the use of a lever! ! ! (2012-06-18, VHDL, 5KB, 下载5次)

http://www.pudn.com/Download/item/id/1916509.html

[VHDL/FPGA/Verilog] DF2C8_01_LED

led 灯的显示，加胆码整体功能。LED deng
led display (2011-12-11, Others, 328KB, 下载3次)

http://www.pudn.com/Download/item/id/1727475.html

[VHDL/FPGA/Verilog] full_add

全加器，可移植性很强，只需要变换一下里面的数字就能得到任意的全加器！
The counter, portability is very strong, only need to a change in the inside of the digital can get any counter!!!!! (2011-08-09, VHDL, 1KB, 下载4次)

http://www.pudn.com/Download/item/id/1618116.html

[VHDL/FPGA/Verilog] alu

本程序实现算术逻辑单元（ALU）设计，包括：清零、逻辑乘、逻辑加、异或、算术加、左移、右移等等功能。
Arithmetic logic unit to achieve the program design, including: clear, logical multiplication, logical add, XOR, arithmetic plus, left, right, and so function (2011-07-21, Others, 78KB, 下载6次)

http://www.pudn.com/Download/item/id/1603088.html

[VHDL/FPGA/Verilog] 1

德萨法阿斯地方顺风萨多夫阿斯顿法萨多夫多少
local wind Saduo Fu (2011-03-15, VHDL, 1KB, 下载2次)

http://www.pudn.com/Download/item/id/1456164.html

[VHDL/FPGA/Verilog] for_ws

裡頭有加法器,全加器,rippple adder
full adder ,rippple adder (2010-01-17, VHDL, 5KB, 下载2次)

http://www.pudn.com/Download/item/id/1043014.html

[VHDL/FPGA/Verilog] Adder4

本设计是设计了一个4位全加器的内容，是由4个一位全加器串联而成的
The design is to design a full adder 4 content, is one of four full adder in series from the (2009-05-11, VHDL, 4KB, 下载5次)

http://www.pudn.com/Download/item/id/754348.html

[VHDL/FPGA/Verilog] Boothmultiplier

布斯乘法器的语言描述功能违反外暗暗达到
Booth multiplier described in the language (2009-03-31, VHDL, 2KB, 下载6次)

http://www.pudn.com/Download/item/id/695915.html

[VHDL/FPGA/Verilog] daima

适用于xilinx的CPLD产品，曼彻斯特编码
Decoder for Xilinx CPLDs Customer Pack (2009-03-02, VHDL, 10KB, 下载9次)

http://www.pudn.com/Download/item/id/658383.html

[VHDL/FPGA/Verilog] four_fadd

这是我在ISP编程实验中独立编写的采用结构化描述的四位全加器，通过四次映射一位全加器的方式实现了四位全加器的功能，并附有数码显示模块，将全加器的运算结果输出到数码管显示。
This is my ISP programming experiment in the preparation of an independent structural description of the four full-adder, through the four mapping of a full adder means four full-adder function, together with a digital display module will be full adder computing the results output to a digital display. (2008-12-21, VHDL, 119KB, 下载3次)

http://www.pudn.com/Download/item/id/611495.html

[VHDL/FPGA/Verilog] manchester_verilog

曼彻斯特编解码Verilog代码非常好的速度快，而且资源占用少。
Manchester codec Verilog code very good speed, but also occupy less resources. (2008-06-13, VHDL, 10KB, 下载151次)

http://www.pudn.com/Download/item/id/489277.html