verilog，arty z7 10，维瓦多
verilog, arty z7 10 , vivado (2024-02-12, VHDL, 0KB, 下载0次)
Nand2俄罗斯方块FPGA
Nand2TetrisFPGA (2024-01-14, Assembly, 0KB, 下载0次)
CARDIO超维计算的实现
A implemention of Hyperdimensional Computing for CARDIO (2021-04-28, SystemVerilog, 1476KB, 下载0次)
俄罗斯方块游戏，采用Verilog编写，整个工程文件，TFT/VGA显示
Tetris game, written by Verilog, the whole project file, TFT / VGA display (2019-12-15, Verilog, 4502KB, 下载2次)
16个常用HDL编码打包上传 包括记数器，多路选择器，全加/半加器等，均通过modsim验证
16 commonly used HDL coding package upload includes counter, MUX, all add/semi-add, etc., are adopted to verify modsim (2014-05-21, Visual C++, 4KB, 下载1次)
基于FPGA的由两个四位全加器合成的八位全加器
Based on the synthesis of two four eight full adder full adder FPGA (2014-03-28, VHDL, 420KB, 下载8次)
16个常用HDL编码打包上传 包括记数器，多路选择器，全加/半加器等，均通过modsim验证
16 commonly used HDL coding package upload includes counter, MUX, all add/semi-add, etc., are adopted to verify modsim (2013-12-29, Visual C++, 4KB, 下载2次)
自适应维纳FIR滤波器消除脑电波中的干扰，请高手指教
Adaptive Wiener FIR filter brain waves to eliminate the interference, experts advise (2013-08-18, matlab, 4KB, 下载8次)
基于VHDL语言的HD4069曼彻斯特编码器实现
Based on VHDL HD4069 Manchester encoder implementation (2013-01-29, VHDL, 168KB, 下载15次)
基于FPGA的俄罗斯方块VHDL逻辑代码，通过VGA显示在液晶屏幕上，基本功能完全实现
VHDL logic code Tetris FPGA-based VGA display on the LCD screen, the basic functions of the full realization of (2012-11-06, VHDL, 3759KB, 下载77次)
曼彻斯特编解码~VHDL?顾固乇嘟嘟饴雫VHDL曼彻斯特编解码~VHDL
Manchester encoding and decoding ~~ VHDL? Gu solid Torr toot-yee, Shizukuishi VHDL Manchester Manchester codec ~ VHDL (2012-07-22, Visual C++, 10KB, 下载5次)
8*8的乘法器，其中使用了门电路和全加器来实现的，全加器用以实现进位运算，
8* 8 multiplier, which uses the gate and full adder to implement the full adder to achieve binary operations (2012-07-12, VHDL, 2KB, 下载3次)
8*8点阵实现俄罗斯方块功能，左移右移以及消行
8* 8 dot matrix Tetris (2012-06-12, VHDL, 1076KB, 下载6次)
基于FPGA 的全加器设计。应用软件是Qartaus 2
full_adder design (2012-04-24, VHDL, 250KB, 下载4次)
用Verilog写的小游戏，俄罗斯方块,在VGA上实现游戏功能
Verilog game (2010-08-23, Others, 8483KB, 下载488次)
lcd12864 全屏显示
汉字加字符
lcd12864 full screen characters plus characters (2010-05-28, VHDL, 1KB, 下载10次)
布斯乘法器 这种特殊的乘法器供给需要使用的人使用
Booth multiplier (2010-05-19, VHDL, 2KB, 下载1次)
八位加法器的原理图实现方法和一位半加器 全加器的原理图实现
Eight adder schematic diagram of the method and a half adder full adder schematic diagram of the realization of (2009-06-07, VHDL, 268KB, 下载4次)
一位全加器源码实现了MAX及其一系列器件实现全加的功能
A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian (2009-04-25, VHDL, 13KB, 下载6次)
此曼彻斯特码的解码程序是采用VHDL硬件语言编写的。
this procedure code decoder VHDL hardware is used to prepare the language. (2005-09-24, WORD, 3KB, 下载87次)