[LabView编程] labview-拉普拉斯变换
基于labview的信号的拉普拉斯变换，希望对你有所帮助。
Laplace transform of signal based on LabVIEW, hope to help you. (2020-09-16, VHDL, 10KB, 下载9次)
[VHDL/FPGA/Verilog] ParallelAdder
基于VHDL语言的并行全加器，包含测试文件
Parallel Adder based on VHDL, testbench included (2020-05-30, VHDL, 941KB, 下载0次)
[VHDL/FPGA/Verilog] f_adder
在Quartus II 中 以原理图输入的方法实现一位全加器，其中包括一位半加器元件的例化，以及波形仿真文件。
In Quartus II, a full adder is realized by schematic input, including the instantiation of a half adder element. (2018-12-08, VHDL, 5673KB, 下载0次)
[VHDL/FPGA/Verilog] 32bit_add_exercise
32位全加器，另有一个采用流水线的版本，是基于verilog语言的，很实用，希望对大家有所帮助
32-bit full adder, while a pipelined version，code is based on verilog language, it is practical, we hope to help (2016-07-19, VHDL, 3710KB, 下载3次)
[VHDL/FPGA/Verilog] AES-pipelined-architecture
AES算法，采用FPGA实现，重点描述了流水线设计，使用才方法使加解密具有很高的吞吐率
An AES crypto chip using a high-speed parallel pipelined architecture (2014-12-31, VHDL, 348KB, 下载4次)
[VHDL/FPGA/Verilog] basketball-counter
篮球机分区，显示两个队的得分分为两个方向积分，每次加1或者减1
basketball counter (2013-05-15, VHDL, 5KB, 下载2次)
[单片机开发] LEDliudong
跑马灯，让八个led灯循环的点亮，里面主要是使用了分频加计数
through water (2012-11-25, VHDL, 295KB, 下载5次)
[VHDL/FPGA/Verilog] all-add
全加器的原理和代码。不过原理图我也做好了，有时间在传上。。
thank you (2012-11-01, VHDL, 32KB, 下载2次)
[VHDL/FPGA/Verilog] pld_Tetris
基于FPGA cyclone III EP3C16F484C6的俄罗斯方块游戏。实现双人进行，屏幕倒置，分数显示，vga接口，键盘接口等功能
Tetris game based on FPGA cyclone III EP3C16F484C6 with functions including double players, screen upside down, score, vga and keyboard interface. (2012-07-13, VHDL, 626KB, 下载54次)
[VHDL/FPGA/Verilog] 09081113
简单计数器，分频器，全加器等vhdl程序等
Simple counter, divider, adder vhdl procedures such as (2011-11-27, VHDL, 2802KB, 下载3次)
[VHDL/FPGA/Verilog] adder
用VHDL语言编写的全加器文件 希望对大家有所帮助 原创空间 大家多多支持
failed to translate (2011-10-26, VHDL, 3KB, 下载2次)
[VHDL/FPGA/Verilog] four
大学VHDL实验科目报告四位全加器设计报告
University of VHDL test subjects reported four full adder design report (2011-06-24, VHDL, 203KB, 下载4次)
[VHDL/FPGA/Verilog] Full.adder
Verilog的RTL级别全加器和测试平台，测试通过
Verilog RTL level full adder and test benck (2011-01-17, VHDL, 1KB, 下载10次)
[VHDL/FPGA/Verilog] waveletcg_example
一维小波变换一层重构，实现MALLAT算法重构，经测试完全正确。
Layer of one-dimensional wavelet transform reconstruction algorithm to achieve MALLAT reconstruction, tested entirely correct. (2010-11-05, VHDL, 1664KB, 下载56次)
[VHDL/FPGA/Verilog] clock_counter
一个简易的时分秒自加计数器，没有设置功能
hour-minute-second counter (2010-01-13, VHDL, 2KB, 下载5次)
[VHDL/FPGA/Verilog] subadd
一个四位二进制加/减运算器。
要求：当控制端G＝0时做加运算，G＝1时做减运算。用发光二极管表示运算结果的正、负。用数码管显示运算结果：加运算时，相加之和不超过15，减运算时，结果可正可负，但都用原码表示。
Plus a four binary/by calculator. Requirements: When the control terminal G = 0 when computing increases, G = 1 when computing reduced. Computing with light-emitting diodes, said the results of positive and negative. Digital display computing Results: Canadian operations, the sum of not more than 15, by calculation, the result can be negative now, but they said the original code. (2009-04-29, VHDL, 219KB, 下载44次)
[嵌入式/单片机/硬件编程] fulladder
这是一个基于嵌入式的利用硬件高级描述语言编写的全加器程序，可以满足二进制全加的功能。
This is a use of embedded hardware-based high-level language to describe the All-Canadian program to meet the functions of the binary full adder. (2009-04-21, VHDL, 179KB, 下载2次)
[VHDL/FPGA/Verilog] vhdl
VHDL的实例加解说,对初学习者用处很大的!
something using of VHDL,very useful. (2009-03-26, VHDL, 17908KB, 下载6次)
[VHDL/FPGA/Verilog] fourbitincrement
用VHDL编译的源代码，4bit加一器，输入一个4位二进制数自动加一，解压后直接用Quartus打开project即可
Compiled with VHDL source code, 4bit-plus-one, and enter a 4-bit binary number plus one automatically, after extracting the direct use of Quartus can open the project (2008-11-04, VHDL, 243KB, 下载2次)
[VHDL/FPGA/Verilog] inc
0到9加计数
9到0减计数
0-9 plus 9-0 count by count (2008-05-23, VHDL, 24KB, 下载4次)