利用Montgomery模乘法器实现RSA加解密的VHDL实现
VHDL implementation of RSA encryption decryption using Montgomery modular multipliers (2016-04-15, VHDL, 1299KB, 下载0次)
实现2位2进制加法器,以及全加器的modelsim仿真
Implementation of 2-bit 2-ary adder (2021-03-23, VHDL, 69KB, 下载0次)
利用quartus9.0编写的半加器程序，自己亲手设计，能有效运行出结果
Quartus9.0 prepared by the semi adder program, personally designed to effectively run the results (2017-06-28, VHDL, 77KB, 下载1次)
注意：是verilog语言写的
一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加
Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder (2016-05-03, VHDL, 521KB, 下载9次)
全加器：Powerpoint课件示例支持，典型组合逻辑原理图输入设计
full adder design with VHDL (2015-03-12, VHDL, 58KB, 下载1次)
七人表决器，利用全加器设计。当有四人或四人以上表决同意，实验箱上的指示灯亮
Seven people voting, the use of full adder design. When there are four or more than four agreed to vote on the bright lights test box (2015-01-17, VHDL, 127KB, 下载1次)
VHDL实现俄罗斯方块，有难度设置，vga输出ps2输入
VHDL realization of Tetris, have difficulty settings, vga output ps2 input (2014-12-06, VHDL, 10263KB, 下载17次)
基于VHDL实现俄罗斯方块游戏，vga输出 ps2输入
VHDL-based Tetris game, vga output ps2 input (2014-12-06, VHDL, 2141KB, 下载10次)
8 位全加器的设计，采用多pipeline设计方法
8 full adder multi-pipeline design (2013-10-26, VHDL, 795KB, 下载3次)
使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮
A full adder design (2013-09-26, VHDL, 1KB, 下载2次)
用verilog编写的科斯塔斯环，希望有帮助
Costas loop written in verilog helpful (2012-10-31, VHDL, 1KB, 下载78次)
全加器，比较器等verilog hdl代码 以及测试代码
Full adder verilog hdl code of the comparator (2012-05-15, VHDL, 1KB, 下载3次)
VHDL设计8位算术逻辑单元（alu），实现清零、逻辑乘、逻辑加、逻辑异或、算术加、逻辑左移一位、逻辑右移一位等功能
VHDL design eight the arithmetic/logic unit (alu), realize the reset, logic, logic and, by different or, arithmetic and logic, logical moves left a, logic move to the right a etc. (2011-12-08, VHDL, 1451KB, 下载23次)
用FPGA驱动VGA显示器并控制VGA显示部分俄罗斯方块以及横条、竖条、棋盘格等
Driving with FPGA VGA VGA display and control the display part of the Russian box and bar, vertical bar, checkerboard, etc. (2010-10-03, VHDL, 1160KB, 下载96次)
用Verilog HDL 实现的4位二进制全加器。
4-bit full adder implemented with Verilog HDL (2010-03-31, VHDL, 1KB, 下载4次)
曼彻斯特编解码的实现（Verilog）,包含有测试文件。
manchester encode and decode with verilog，Test File is included。 (2009-11-27, VHDL, 10KB, 下载36次)
几十个经典程序，结构描述的4 位级连全加器，1 位全加器，用条件运算符描述的4 选1 MUX等等
Dozens of classic procedure, the structure described in the four-level with full-adder, a full-adder, using the conditional operator described in the four selected 1 MUX, etc. (2009-10-12, VHDL, 4KB, 下载6次)
实现一个加/减8进制计数器。其中包括时钟输入、使能信号、加减控制信
号、复位信号、三位输入和一位进位位。
To achieve a plus/minus 8 binary counter. These include the clock input enable signal, addition and subtraction control signals, reset signals, three inputs and a carry bit. (2009-09-02, VHDL, 32KB, 下载24次)
使用Vhdl语言实现数字电路全加器功能，算法比较简单，供初学者参考。
full adder (2009-03-06, VHDL, 30KB, 下载42次)
加解密的一个方案了,关于"椭圆"的理论和算法
Encryption and decryption of a program, and on the (2008-08-09, VHDL, 399KB, 下载3次)