2020锡林克斯暑期学校
2020 Xilinx summer school (2022-03-20, VHDL, 40524KB, 下载0次)
fpga的入门教程,加ise软件使用教程
Introductory tutorials of fpga and software usage tutorials of ise (2019-04-08, VHDL, 3256KB, 下载1次)
用quartus设计的全加器,包含RTL电路图
The full adder designed by quartus includes RTL circuit diagram. (2018-08-27, VHDL, 2767KB, 下载0次)
布斯,阵列乘法器,加减交替除法器,以及ROM存储器,FIFO存储器
Booth, array multiplier, divider alternately add and subtract, and ROM memory, FIFO memory (2015-10-16, VHDL, 19KB, 下载2次)
完成功能科斯塔斯环,内有完整工程文件,希望能对您有所帮助
Completion Costas loop, within a complete engineering documents, hoping to be helpful to you (2015-09-11, VHDL, 1653KB, 下载11次)
曼切斯特码解码器verilog程序,已通过ModelSIM仿真,可用
Chester Verilog decoder procedures, has been through the ModelSIM simulation, the available (2015-02-06, VHDL, 1KB, 下载3次)
VHDL时钟芯片设计,走时加显示,用于XC3S50-TQ144,引脚已定义,可直接载入运行
VHDL clock design with display (2014-03-18, VHDL, 1314KB, 下载5次)
简明的DES密码算法的VHDL代码,实现了基本的加脱密
Condensed DES cryptographic algorithm VHDL code, basic plus decryption (2013-03-04, VHDL, 5KB, 下载2次)
基于FPGA的半加器源码,声明,有verilog编写的
FPGA-based half adder source, statement, written in verilog (2012-09-27, VHDL, 240KB, 下载3次)
两位运算器,实现俩位加、减、乘、除基本功能。并能实现移位功能
The two computing device (2012-05-10, VHDL, 3KB, 下载3次)
俄罗斯方块程序,Xilinx开发板,芯片型号Spartan3E,PQ208,用VHDL语言编写
Tetris program, Xilinx development board, chip type Spartan3E, PQ208, using VHDL language (2011-12-27, VHDL, 4224KB, 下载22次)
这个程序为汉明码的编码与解码,程序中有加错与纠错的环节,简单易懂
hamming coding decoding (2011-05-31, VHDL, 415KB, 下载21次)
用VHDL语言设计了一个8位2进制全加器
VHDL language design with an 8-bit binary full adder 2 (2010-11-30, VHDL, 169KB, 下载6次)
全加器源代码,VHDL语言编写,有需要的参考参考
Full adder source code, VHDL language, the need to reference information (2010-05-12, VHDL, 117KB, 下载6次)
一位加法全加器,可以实现低位进位输入和高位进位输出。
full adder (2009-12-24, VHDL, 77KB, 下载6次)
秒表功能的显示
LCD1602显示,自动加1
VHDL
SECOND WATCH
测试通过 (2009-05-25, VHDL, 29KB, 下载33次)
用VHDL语言实现半加器。已经通过编译和仿真
Implementation using VHDL language half adder. Has passed the compiler and simulation (2009-03-05, VHDL, 138KB, 下载2次)
完成一个加速器设计,全加器,具 8位计数器
Complete a accelerator design, full adder, an 8-bit counter (2008-12-25, VHDL, 1KB, 下载3次)
將DE2連接到LCD版面上
內為友晶客科技公司所附製的程式碼
DE2 will connect to the LCD layout for Terasic off technology companies attached to the system code (2008-10-17, VHDL, 659KB, 下载50次)
用Verilog HDL实现的曼彻斯特编码器和解码器。
Using Verilog HDL realize the Manchester encoder and decoder. (2008-04-13, VHDL, 9KB, 下载249次)