[VHDL/FPGA/Verilog] fpga-tetris
fpga俄罗斯方块
fpga tetris (2024-02-22, C, 0KB, 下载0次)
[VHDL/FPGA/Verilog] openFPGA-MarioBros
openFPGA马里奥布罗斯
openFPGA MarioBros (2024-02-13, VHDL, 0KB, 下载0次)
[VHDL/FPGA/Verilog] DE2_VGA3
使用DE2开发板的VGA模块，来仿真实现一维元胞自动机。
The VGA module of DE2 development board is used to simulate and realize one-dimensional cellular automata. (2019-04-21, Verilog, 1645KB, 下载0次)
[VHDL/FPGA/Verilog] f_adder
在Quartus II 中 以原理图输入的方法实现一位全加器，其中包括一位半加器元件的例化，以及波形仿真文件。
In Quartus II, a full adder is realized by schematic input, including the instantiation of a half adder element. (2018-12-08, VHDL, 5673KB, 下载0次)
[VHDL/FPGA/Verilog] 32bit_add_exercise
32位全加器，另有一个采用流水线的版本，是基于verilog语言的，很实用，希望对大家有所帮助
32-bit full adder, while a pipelined version，code is based on verilog language, it is practical, we hope to help (2016-07-19, VHDL, 3710KB, 下载3次)
[VHDL/FPGA/Verilog] PINGPANGQIU
实现乒乓球的简单功能,一对没接到球,二队加一分,二队如果没接到球,二队加一分
A simple function for table tennis match, a pair of missed the ball, add one point, second team if the team missed the ball, a pair of a point (2015-06-10, Asm, 26KB, 下载2次)
[VHDL/FPGA/Verilog] mac_t
曼彻斯特编解码，有助于学习和开发，适合大家使用
Manchester codec, to help learn and develop, for everyone to use (2015-06-01, VHDL, 550KB, 下载1次)
[VHDL/FPGA/Verilog] AES-pipelined-architecture
AES算法，采用FPGA实现，重点描述了流水线设计，使用才方法使加解密具有很高的吞吐率
An AES crypto chip using a high-speed parallel pipelined architecture (2014-12-31, VHDL, 348KB, 下载4次)
[VHDL/FPGA/Verilog] 4.2
曼切斯特编码，解码Verilog源代码
nrz,1553协议通信采用的编解码方式
Manchester encoding, decoding, Verilog source code (2014-09-29, Others, 97KB, 下载38次)
[VHDL/FPGA/Verilog] adder
这是一个最简单的四位的全加器设计，由两个半加器构成，采用的是VERILOG的算法级和门级描述的。
This is one of the easiest of the four full adder design, consists of two half-adder, the VERILOG algorithm-level and gate-level descriptions. (2013-05-14, VHDL, 165KB, 下载2次)
[VHDL/FPGA/Verilog] tetis
用verilog编写的俄罗斯方块游戏，适合初学者
Tetris game written in verilog for beginners (2012-12-15, VHDL, 17942KB, 下载2252次)
[VHDL/FPGA/Verilog] booth_mult
布斯乘法器的verilog实现及仿真文件,使用modelsim仿真
booth mult s verilog and test (2012-03-27, DOS, 1KB, 下载15次)
[VHDL/FPGA/Verilog] waveletcg_example
一维小波变换一层重构，实现MALLAT算法重构，经测试完全正确。
Layer of one-dimensional wavelet transform reconstruction algorithm to achieve MALLAT reconstruction, tested entirely correct. (2010-11-05, VHDL, 1664KB, 下载56次)
[VHDL/FPGA/Verilog] Booth_Multiplier
布斯乘法器,适用于VHDL语言操作,对于初学者或是深入的人都适宜
Booth Multiplier (2009-07-07, VHDL, 2KB, 下载9次)
[VHDL/FPGA/Verilog] mqst
基于CPLD的数字通信系统曼切斯特用VHDL产生 曼切斯特信号
CPLD-based digital communications system Manchester Manchester signal generated by VHDL (2009-05-16, VHDL, 3KB, 下载13次)
[VHDL/FPGA/Verilog] fourbitincrement
用VHDL编译的源代码，4bit加一器，输入一个4位二进制数自动加一，解压后直接用Quartus打开project即可
Compiled with VHDL source code, 4bit-plus-one, and enter a 4-bit binary number plus one automatically, after extracting the direct use of Quartus can open the project (2008-11-04, VHDL, 243KB, 下载2次)
[VHDL/FPGA/Verilog] DCT_1D
一维DCT变换的verilog源码，可用于JPEG算法优化的参考。程序中用到的算法称为“扭卷积”，可参考相关IEEE paper
One-dimensional DCT transform Verilog source code can be used to optimize the JPEG algorithm reference. Procedures used in the algorithm known as the (2007-10-25, Others, 53KB, 下载71次)
[VHDL/FPGA/Verilog] 10vhdlexamples
10个VHDL程序实例，包括加法器，全加器、函数发生器，选择器等。
10 examples of VHDL procedures, including the adder, full adder, function generator, selector and so on. (2007-07-30, Others, 41KB, 下载55次)
[VHDL/FPGA/Verilog] cpldcodec
用CPLD控制曼彻斯特编解码器，很详细的文字说明。
with CPLD control of Manchester codecs, very detailed notes. (2007-01-15, Others, 119KB, 下载83次)
[VHDL/FPGA/Verilog] Booth_Multiplier
布斯乘法器的VHDL程序,下載後直接解壓縮複製貼上到你的EDATOOL就可以.
Booth multiplier VHDL procedures downloaded directly extract copy affixed to the EDATOOL you can. (2006-04-06, MultiPlatform, 1KB, 下载72次)