[VHDL/FPGA/Verilog] RSA_on_FPGA
RSA加解密的硬件实现，在FPGA上测试
Hardware implementation of RSA Encryption Decryption, tested on FPGA (2019-09-23, SystemVerilog, 8KB, 下载0次)
[VHDL/FPGA/Verilog] ParallelAdder
基于VHDL语言的并行全加器，包含测试文件
Parallel Adder based on VHDL, testbench included (2020-05-30, VHDL, 941KB, 下载0次)
[VHDL/FPGA/Verilog] Verilog俄罗斯方块
本设计是verilog设计的俄罗斯方块，含有所有的源代码。
This design is Verilog designed Tetris, which contains all the source code. (2018-07-30, Verilog, 8618KB, 下载1次)
[VHDL/FPGA/Verilog] pine_line_adder8
8 位全加器的设计，采用多pipeline设计方法
8 full adder multi-pipeline design (2013-10-26, VHDL, 795KB, 下载3次)
[VHDL/FPGA/Verilog] or2a
使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮
A full adder design (2013-09-26, VHDL, 1KB, 下载2次)
[VHDL/FPGA/Verilog] basketball-counter
篮球机分区，显示两个队的得分分为两个方向积分，每次加1或者减1
basketball counter (2013-05-15, VHDL, 5KB, 下载2次)
[VHDL/FPGA/Verilog] all-add
全加器的原理和代码。不过原理图我也做好了，有时间在传上。。
thank you (2012-11-01, VHDL, 32KB, 下载2次)
[VHDL/FPGA/Verilog] pld_Tetris
基于FPGA cyclone III EP3C16F484C6的俄罗斯方块游戏。实现双人进行，屏幕倒置，分数显示，vga接口，键盘接口等功能
Tetris game based on FPGA cyclone III EP3C16F484C6 with functions including double players, screen upside down, score, vga and keyboard interface. (2012-07-13, VHDL, 626KB, 下载54次)
[VHDL/FPGA/Verilog] 09081113
简单计数器，分频器，全加器等vhdl程序等
Simple counter, divider, adder vhdl procedures such as (2011-11-27, VHDL, 2802KB, 下载3次)
[VHDL/FPGA/Verilog] adder
用VHDL语言编写的全加器文件 希望对大家有所帮助 原创空间 大家多多支持
failed to translate (2011-10-26, VHDL, 3KB, 下载2次)
[VHDL/FPGA/Verilog] four
大学VHDL实验科目报告四位全加器设计报告
University of VHDL test subjects reported four full adder design report (2011-06-24, VHDL, 203KB, 下载4次)
[VHDL/FPGA/Verilog] Full.adder
Verilog的RTL级别全加器和测试平台，测试通过
Verilog RTL level full adder and test benck (2011-01-17, VHDL, 1KB, 下载10次)
[VHDL/FPGA/Verilog] banjiaqi_t15
这是个半加器,是基于VHDL语言上的操作来实现的!
this is a banjiaqi (2010-12-19, Visual C++, 130KB, 下载3次)
[VHDL/FPGA/Verilog] FPGA1
4位全加器 仿真波形一点问题都没有 我调试过
ADD (2010-05-15, Visual C++, 182KB, 下载7次)
[VHDL/FPGA/Verilog] ex1.v
用Verilog HDL 实现的4位二进制全加器。
4-bit full adder implemented with Verilog HDL (2010-03-31, VHDL, 1KB, 下载4次)
[VHDL/FPGA/Verilog] clock_counter
一个简易的时分秒自加计数器，没有设置功能
hour-minute-second counter (2010-01-13, VHDL, 2KB, 下载5次)
[VHDL/FPGA/Verilog] subadd
一个四位二进制加/减运算器。
要求：当控制端G＝0时做加运算，G＝1时做减运算。用发光二极管表示运算结果的正、负。用数码管显示运算结果：加运算时，相加之和不超过15，减运算时，结果可正可负，但都用原码表示。
Plus a four binary/by calculator. Requirements: When the control terminal G = 0 when computing increases, G = 1 when computing reduced. Computing with light-emitting diodes, said the results of positive and negative. Digital display computing Results: Canadian operations, the sum of not more than 15, by calculation, the result can be negative now, but they said the original code. (2009-04-29, VHDL, 219KB, 下载44次)
[VHDL/FPGA/Verilog] vhdl
VHDL的实例加解说,对初学习者用处很大的!
something using of VHDL,very useful. (2009-03-26, VHDL, 17908KB, 下载6次)
[VHDL/FPGA/Verilog] fulladder
使用Vhdl语言实现数字电路全加器功能，算法比较简单，供初学者参考。
full adder (2009-03-06, VHDL, 30KB, 下载42次)
[VHDL/FPGA/Verilog] inc
0到9加计数
9到0减计数
0-9 plus 9-0 count by count (2008-05-23, VHDL, 24KB, 下载4次)