XILINX-斯巴达6-采样率转换器
XILINX - Spartan 6 - Sample Rate Converter (2015-07-24, VHDL, 157KB, 下载0次)
布莱克-斯科尔斯式期权定价采用蒙特卡罗方法。用VHDL为Cyclone IV FPGA板编写。
Black-Scholes style options pricing using Monte Carlo methods. Written in VHDL for the Cyclone IV FPGA board. (2015-06-10, VHDL, 2883KB, 下载0次)
8bit全加器的VHDL代码实现，可以配合simulink进行仿真。
The VHDL code implementation of 8 bit full adder can be simulated with simulink. (2019-03-30, VHDL, 1KB, 下载0次)
4位booth算法乘法器，用Verilog编写
4-bit Booth algorithm multiplier (2018-12-07, VHDL, 1KB, 下载12次)
加按键程序,有助于vhdl语言的初级学习!可以下载看看.
Plus key procedures, contribute to the VHDL language the primary learning! Can download to see. (2013-04-29, VHDL, 27KB, 下载3次)
组合逻辑全加器，在vhdl环境下的，我试过，可以运行。
The combinational logic full adder in VHDL environment, I tried, you can run. (2013-04-25, VHDL, 749KB, 下载4次)
四位全加器，是自己编写的，如有错误，请原谅
I have written four full adder, is subject to error, please forgive (2012-11-17, VHDL, 39KB, 下载3次)
通过调用被实例化的模块来实现四位全加器功能
Four full adder function is achieved by calling the module is instantiated (2012-11-08, VHDL, 1KB, 下载3次)
veriog 实现求逆模块 加仿真结果 shi henyong
verilog is useful in finite field (2012-06-22, VHDL, 25KB, 下载27次)
4 级流水方式的8 位全加器 vhdl 语音那描述
The level 4 water way QuanJia 8 bits for speech that described VHDL (2012-04-18, VHDL, 248KB, 下载4次)
在FPGA开发板上实现俄罗斯方块游戏的功能，可以链接电脑显示器并使用电脑键盘来控制。
A Tetris game based on FPGA (2012-03-22, VHDL, 1405KB, 下载288次)
i2c总线控制协议，一共五个v文件。没有加外部io
i2c bus control protocol, a total of five v file. No additional external io (2011-11-16, VHDL, 12KB, 下载3次)
verilog verilog+十大基本功能 很实用，入门加提高，经验
verilog verilog+ ten basic functions very practical, entry-plus increase, experience (2011-08-10, VHDL, 1599KB, 下载10次)
DFF1开发 半加器 超好用的 不信你们试一试呀
DFF1 development of half adder Chaohaoyong do not believe you try ah (2011-07-17, VHDL, 1KB, 下载3次)
用硬件描述语言编写的8位全加器代码，很实用！
Using hardware description language preparation 8 bits QuanJia implement code, very useful!! (2011-01-21, VHDL, 1KB, 下载3次)
此源代码是基于Verilog语言的多种方式实现的4 选 1 MUX、多种方式实现的4 选 2 MUX 、多种方式实现的1 位半加器 、多种方式实现的1 位全加器、种方式实现的 4 位全加器 、多种方式实现的输出 UDP 元件、两个时钟信号 、选择器 和各种仿真的源代码。
This source code is based on the Verilog language, multiple ways to achieve the 4 S 1 MUX, a variety of ways to achieve the 4 S 2 MUX, a variety of ways to achieve a half adder, a variety of ways to achieve a full adder, ways to achieve the 4-bit full adder, the output of a variety of ways to achieve UDP component, two clock signals, the selector and a variety of simulation source code. (2010-10-30, VHDL, 4KB, 下载7次)
VHDL实验一，利用原理图输入法设计4位全加器
VHDL test 1, use of schematic input 4-bit full adder design (2010-04-01, VHDL, 484KB, 下载6次)
Nios复旦教程，想学习SOPC的，要仔细研究啊，另附加Nios常用函数。
nios sopc nios_function (2009-03-11, VHDL, 3668KB, 下载64次)
manchester码在通信领域中用途广泛
这个VHDL程序包括曼彻斯特码的打包和解包。。很难得哦
manchester code in the communications area of a wide range of uses of this process includes the VHDL code packaged Manchester reconciliation package. . Oh, a rare (2009-02-17, VHDL, 1KB, 下载99次)
加法器
用VerilogHDL实现加罗华域加法器
Used realize adder VerilogHDL Le Hua domain adder (2008-07-09, VHDL, 189KB, 下载9次)