艾斯计算机
Eis Computer (2023-04-26, C, 1126KB, 下载0次)
利用Montgomery模乘法器实现RSA加解密的VHDL实现
VHDL implementation of RSA encryption decryption using Montgomery modular multipliers (2016-04-15, VHDL, 1299KB, 下载0次)
实现2位2进制加法器,以及全加器的modelsim仿真
Implementation of 2-bit 2-ary adder (2021-03-23, VHDL, 69KB, 下载0次)
移位寄存器模块用于存储串行输入滤波器的数据；乘加计算模块用于fir计算
The shift register module is used to store data of serial input filter, and the multiplier calculation module is used for FIR calculation. (2018-06-30, Verilog, 1KB, 下载3次)
利用quartus9.0编写的半加器程序，自己亲手设计，能有效运行出结果
Quartus9.0 prepared by the semi adder program, personally designed to effectively run the results (2017-06-28, VHDL, 77KB, 下载1次)
注意：是verilog语言写的
一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加
Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder (2016-05-03, VHDL, 521KB, 下载9次)
熟悉VHDL元件例化语句的作用
熟悉全加器的工作原理
用VHDL语言设计一位二进制全加器，并仿真。
The role of components instantiated. Familiar with VHDL statements
Familiar with the working principle of full adder
Using VHDL language to design a binary full adder, and simulation.
(2015-03-10, HTML, 9KB, 下载2次)
七人表决器，利用全加器设计。当有四人或四人以上表决同意，实验箱上的指示灯亮
Seven people voting, the use of full adder design. When there are four or more than four agreed to vote on the bright lights test box (2015-01-17, VHDL, 127KB, 下载1次)
VHDL实现俄罗斯方块，有难度设置，vga输出ps2输入
VHDL realization of Tetris, have difficulty settings, vga output ps2 input (2014-12-06, VHDL, 10263KB, 下载17次)
基于VHDL实现俄罗斯方块游戏，vga输出 ps2输入
VHDL-based Tetris game, vga output ps2 input (2014-12-06, VHDL, 2141KB, 下载10次)
用verilog编写的科斯塔斯环，希望有帮助
Costas loop written in verilog helpful (2012-10-31, VHDL, 1KB, 下载78次)
数码相框，tft彩屏加SDHC，读取SDHC卡里面的图片在TFT彩屏上显示
sdhc program (2012-03-20, Others, 85KB, 下载8次)
VHDL设计8位算术逻辑单元（alu），实现清零、逻辑乘、逻辑加、逻辑异或、算术加、逻辑左移一位、逻辑右移一位等功能
VHDL design eight the arithmetic/logic unit (alu), realize the reset, logic, logic and, by different or, arithmetic and logic, logical moves left a, logic move to the right a etc. (2011-12-08, VHDL, 1451KB, 下载23次)
用FPGA驱动VGA显示器并控制VGA显示部分俄罗斯方块以及横条、竖条、棋盘格等
Driving with FPGA VGA VGA display and control the display part of the Russian box and bar, vertical bar, checkerboard, etc. (2010-10-03, VHDL, 1160KB, 下载96次)
曼彻斯特编解码的实现（Verilog）,包含有测试文件。
manchester encode and decode with verilog，Test File is included。 (2009-11-27, VHDL, 10KB, 下载36次)
几十个经典程序，结构描述的4 位级连全加器，1 位全加器，用条件运算符描述的4 选1 MUX等等
Dozens of classic procedure, the structure described in the four-level with full-adder, a full-adder, using the conditional operator described in the four selected 1 MUX, etc. (2009-10-12, VHDL, 4KB, 下载6次)
实现一个加/减8进制计数器。其中包括时钟输入、使能信号、加减控制信
号、复位信号、三位输入和一位进位位。
To achieve a plus/minus 8 binary counter. These include the clock input enable signal, addition and subtraction control signals, reset signals, three inputs and a carry bit. (2009-09-02, VHDL, 32KB, 下载24次)
信号处理FPGA实现参考,IEEE transaction 的一篇文章。主要针对信号处理中加窗、FFT、VSLI快速实现中误差地等问题。
FPGA realization of a reference signal processing, IEEE transaction of an article. Mainly for signal processing windowing, FFT, VSLI rapid error problems. (2008-12-21, PDF, 301KB, 下载18次)
一个用VHDL语言编写的全加器，是数字电路EDA设计的一个例子，可能不太特别，但是应该可以用一下的。
a VHDL prepared by the full adder, digital circuit design of an EDA example, may not be special, but should be able to use what they are doing. (2006-11-28, Others, 16KB, 下载156次)
该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。
the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder. (2005-11-15, Unix_Linux, 21KB, 下载19次)