[VHDL/FPGA/Verilog] source
qdr2的verilog源代码，莱蒂斯FPGA
qdr2 verilog LATTICE FPGA (2017-04-24, VHDL, 16KB, 下载3次)
[VHDL/FPGA/Verilog] TEST1
在本实验中，用三个按键开关来表示 1 位全加器的三个输入（ Ai、 Bi、 Ci）；
用二个 LED 来表示 1 位全加器的二个输出（ Si， C）。通过输入不同的值来观察输
入的结果与 1 位全加器的真值表（表 1-1）是否一致。
In this experiment, three button switches to represent three input a full adder (Ai, Bi, Ci) two by two LED to indicate output a full adder (Si, C). By entering different values and observe the results entered a full-adder truth table (Table 1-1) are the same. (2016-12-27, VHDL, 273KB, 下载1次)
[VHDL/FPGA/Verilog] 2.adder
基于VHDL的全加器时间延迟分析，分析基本器件的传输延迟和惯性延迟
the analysis of timing delay of full adder in VHDL (2015-05-03, VHDL, 135KB, 下载2次)
[VHDL/FPGA/Verilog] EX3_LED
完成LED的自加功能，里面包含完整的说明和测试文件
Complete self-plus-function LED, which contains complete instructions and test files (2015-04-14, VHDL, 3140KB, 下载1次)
[VHDL/FPGA/Verilog] FA
使用VERILOG實現全加器的設計,並附上TB供測試
Use VERILOG achieve full adder design, together with a test for TB (2014-07-07, VHDL, 1KB, 下载2次)
[VHDL/FPGA/Verilog] lab16
数字式秒表大实验的设计代码,并附加测试代码
Digital stopwatch big experiment design code and test code attached (2014-05-07, VHDL, 33KB, 下载8次)
[VHDL/FPGA/Verilog] VHDLbasic_cal
VHDL的加、减、乘、比较等基本运算的源代码
VHDL add, subtract, multiply, compare the source code of the basic operations (2012-09-04, VHDL, 41KB, 下载4次)
[VHDL/FPGA/Verilog] bit1_add
通过使用VHDL语言编写程序实验1位半加器的功能
Through the use of VHDL language programming experiment 1 and a half adder function (2012-02-28, VHDL, 103KB, 下载3次)
[VHDL/FPGA/Verilog] fadder8
基于VHDL语言，编写一个32位全加器文件，可直接编译
Based on VHDL language, write a 32-bit full adder files can be directly compile (2011-12-28, VHDL, 486KB, 下载5次)
[VHDL/FPGA/Verilog] Experiment02
FPGA低级建模试验二流水灯加闪烁等，通过板级调试
FPGA test two low-level flow modeling lamp, flash, etc., by board-level debugging (2011-10-28, VHDL, 118KB, 下载3次)
[VHDL/FPGA/Verilog] AdderE-modelSim
全加器ModelSim工程，modelsim的仿真模型，在quartus下可运行
Full adder ModelSim project, modelsim simulation model can be run under the quartus (2011-10-05, VHDL, 187KB, 下载8次)
[VHDL/FPGA/Verilog] Sainty2
里边有一个半加器。、一个全加器、一个触发器和一个无符号4乘4的乘法器程序，可以完成4位无符号数相乘
Inside there is a half adder. , A full adder, a flip-flop, and an unsigned 4 by 4 multiplier process can be completed by multiplying the number of 4-bit unsigned (2011-06-04, VHDL, 3KB, 下载6次)
[VHDL/FPGA/Verilog] Desktop
曼彻斯特编码的VHDL语言实现，可以用于RFID防碰撞编码的实现
Manchester encoding of the VHDL language, can be used for implementation of RFID anti-collision code (2011-05-12, VHDL, 1KB, 下载15次)
[其他] full_aller
这是基于VHDL的一位全加器设计的程序，分析过程全面
This is based on a full adder VHDL design process, a comprehensive analysis process (2010-04-07, VHDL, 4347KB, 下载10次)
[VHDL/FPGA/Verilog] quartus2-1
QuartusII编程设计一款基于FPDA/QuartusII的计算机部件,可以实现算术运算(加,减,自加1,自减1,乘法,除法)和逻辑运算(与,或,非)等功能!
Based on a QuartusII Programming FPDA/QuartusII the computer components can be achieved Arithmetic (add, subtract, from plus 1, since the minus 1, multiplication, division) and logical operators (and, or, non-) and other functions! (2009-07-20, VHDL, 1989KB, 下载2次)
[VHDL/FPGA/Verilog] fulladder4
VHDL图形文件实现的4位全加器，希望对大家有用！
VHDL graphics files to achieve four full adder, in the hope that useful! (2009-06-24, VHDL, 148KB, 下载2次)
[VHDL/FPGA/Verilog] chap3
全加器和记数器的测试文件，可直接用于modsim测试
Full adder and counter test documents, can be used directly in testing modsim (2009-03-20, VHDL, 5KB, 下载3次)
[VHDL/FPGA/Verilog] add_eight
用VHDL写的一个8位全加器的实验程序,供新手参考
Use VHDL to write an 8-bit full adder of the experimental procedures (2009-02-10, VHDL, 58KB, 下载2次)
[VHDL/FPGA/Verilog] Full_Adder
用VERILOG语言实现了全加器,可综合可仿真通过
Verilog language used to achieve the full adder can be integrated to simulation through (2008-06-01, VHDL, 70KB, 下载3次)
[VHDL/FPGA/Verilog] Project_Navigator_Demo
双向控制全加器的VHDL实现 内含ISE工程文件
Bi-directional control of the full adder VHDL realize intron ISE project file (2008-05-12, VHDL, 107KB, 下载5次)