罗格斯大学嵌入式系统实验室1课程
labs for Rutgers Embedded Systems 1 Course (2024-03-09, VHDL, 0KB, 下载0次)
阿维罗大学可重构计算课程实验室
Labs of the Reconfigurable Computing course, University of Aveiro (2020-06-02, VHDL, 475675KB, 下载0次)
使用vhdl实现spi读取adxl357三轴方向的加速度计值
Using VHDL to realize SPI to read the accelerometer value in three-axis direction of adxl357 (2020-03-06, VHDL, 2KB, 下载4次)
8位二级制乘法，右移输出，有仿真文件。又全加器和移位寄存器构成
8 bit two order multiplication (2018-06-09, VHDL, 300KB, 下载0次)
16进制加、减计数器，用两个数码管显示（0-15）
hex add/sub counter(show 0-15) (2017-07-19, VHDL, 341KB, 下载1次)
本程序是用vhdl开发的实现全加器功能的程序。
This procedure is developed using VHDL to achieve full adder function of the program. (2017-06-07, VHDL, 142KB, 下载1次)
常用的VHDL模块，适合VHDL入门者，本系列一共包含六个VHDL模块，本文件是半加器模块
1.算术逻辑单元（alu_1706）,实现算术逻辑运算
2.CPU寄存器组（cpu_register），实现四个通用寄存器（具有读写功能），一个PC寄存器（清零，置数，加一计数，减一计数，工作使能）。
3.全加器（full_adder）
4.半加器（half_adder）
5.3-8译码器（mutex_3to8）
6.计算机运算器（S6）实现运算器相关功能
VHDL modules commonly used for VHDL beginners, this series contains a total of six VHDL module, arithmetic logic unit (alu_1706), implement arithmetic and logic
2.CPU register set (cpu_register), to realize the four general-purpose registers (read and write functions), a PC register (cleared, set the number, plus one count minus one count, work enabled).
3. The full adder (full_adder)
4. The half-adder (half_adder)
5.3-8 decoder (mutex_3to8)
6. Computer operator (S6) to achieve operator-related functions (2016-05-24, VHDL, 1452KB, 下载1次)
常用的VHDL模块，适合VHDL入门者，本系列一共包含六个VHDL模块，本文件是全加器模块
1.算术逻辑单元（alu_1706）,实现算术逻辑运算
2.CPU寄存器组（cpu_register），实现四个通用寄存器（具有读写功能），一个PC寄存器（清零，置数，加一计数，减一计数，工作使能）。
3.全加器（full_adder）
4.半加器（half_adder）
5.3-8译码器（mutex_3to8）
6.计算机运算器（S6）实现运算器相关功能
VHDL modules commonly used for VHDL beginners, this series contains a total of six VHDL module, arithmetic logic unit (alu_1706), implement arithmetic and logic
2.CPU register set (cpu_register), to realize the four general-purpose registers (read and write functions), a PC register (cleared, set the number, plus one count minus one count, work enabled).
3. The full adder (full_adder)
4. The half-adder (half_adder)
5.3-8 decoder (mutex_3to8)
6. Computer operator (S6) to achieve operator-related functions (2016-05-24, VHDL, 1642KB, 下载1次)
使用Quartus II 9.1完成俄罗斯方块游戏，只要使用有VGA和键盘接口的FPGA开发板就行实现。操作简单，使用的是VHDL和Verilog语言
Use the Quartus II 9.1 to complete the tetris game, as long as you use a VGA and keyboard interface implementation of FPGA development board. The operation is simple, the use of VHDL and the Verilog language (2016-02-17, VHDL, 2126KB, 下载26次)
基于hdl的ofdm基带处理器发射机的设计与实现
包括 工作时钟 主控单元 导频插入 长短训练序列生成 data符号调制 循环前缀与加窗处理 IFFT/FFT 信道编码 扰码模块等
Hdl of ofdm transmitter baseband processor based design and implementation including work clock master unit pilot insertion length of the training sequence generated data symbol modulated cyclic prefix and windowing IFFT/FFT channel coding scrambling module, (2015-05-04, VHDL, 2538KB, 下载28次)
using VHDL language, 是一个用AC97 控制LM4550的系统，可以real-time读听，如果需要录音功能可以直接加一个BRam
VHDL real-time writing-reading system (2012-11-12, VHDL, 2062KB, 下载6次)
用verilog 语言编写的4位全加器，还是入门基础必备.
Verilog language with 4bit full adder, or basic essential.also it s so important to learn verilog! (2012-04-22, VHDL, 1KB, 下载5次)
這是全加器,名字為fulladd4bit.rar,功能為四位元的加法。
This is the full adder, the name of fulladd4bit.rar function is the addition of four bits. (2012-04-17, VHDL, 1KB, 下载3次)
加运算法中的求佘运算。abmodp.generate the control signals for calculating abmodp
Increase in the demand algorithm She operations. abmodp.generate the control signals for calculating abmodp (2011-10-05, VHDL, 2KB, 下载3次)
详细的解析加代码，是用VHDL写的编码器与解码器的简单应用
Plus detailed analysis code is written in VHDL encoder and decoder, a simple application (2011-05-08, VHDL, 97KB, 下载3次)
在QuartusII软件环境下，运用VHDL语言编写的全加器的实现，包含仿真波形
In quartusii software. use vhdl languages of the implementation of a simulation waveforms
(2011-01-07, VHDL, 167KB, 下载3次)
1位全加器，原理图设计，包括波形仿真，和打包，可以直接在Quartus6..0中直接使用
A full adder, schematic design, including the waveform simulation (2010-04-22, VHDL, 149KB, 下载5次)
AES 128bit数据,128bit密钥加解密的verilog语言实现
AES 128bit data, 128bit key encryption and decryption of the verilog language implementation (2010-01-08, VHDL, 78KB, 下载312次)
一种半加器的算法，是基于VHDL软件仿真。请大家下载参考！
A full-adder algorithm is based on the VHDL software emulation. Please download the reference! (2009-09-15, VHDL, 10KB, 下载5次)
verilog 键盘扫描,数码管显示程序，没有加消抖
verilog keyboard scanning, digital tube display program, there is no increase in consumer Buffeting (2009-05-07, VHDL, 1KB, 下载27次)