使用伊维里洛制作并使用Vivado合成的加法器，
Adders made using iverilog and synthesised using Vivado, (2018-10-31, Verilog, 0KB, 下载0次)
基于fpga的nand2俄罗斯方块
nand2tetris on an fpga (2016-08-28, SystemVerilog, 705KB, 下载0次)
基于Box-Mueller方法的FPGA加性高斯白噪声发生器
FPGA Additive White Gaussian Noise Generator Using the Box Mueller Method (2016-10-07, Verilog, 4537KB, 下载0次)
基于FPGA的俄罗斯方块游戏
tetris game on FPGA (2016-06-05, Verilog, 14KB, 下载0次)
带ULX3S的FPGA奥德修斯
FPGA Odysseus with ULX3S (2019-06-04, Verilog, 5114KB, 下载0次)
full adder二位全加器的VHDL代码文件和原理图文件
full adder VHDL code file and schematic file (2020-05-05, VHDL, 275KB, 下载0次)
verilog实现的曼彻斯特和差分曼彻斯特编码。压缩包中有源码和结果截图，代码又注释。
The implementation of Manchester Coding and differential Manchester Coding. The file has the source code and the picture of the result. The code is explanatory. (2017-01-10, Others, 93KB, 下载45次)
基于matlab的iir巴特沃斯的带通滤波器设计，非常好用
Based on the matlab iir Butterworth bandpass filter design, very easy to use (2013-08-23, Others, 1KB, 下载8次)
全加器的硬件描述语言，给出了基础的涉及组成。
Full adder hardware description language, gives the basic components involved. (2013-08-08, VHDL, 221KB, 下载1次)
通过ISE软件采用VHDL语言实现1位全加器的功能
Through the ISE software using VHDL language a full adder function (2013-07-12, VHDL, 3KB, 下载1次)
全加器。VHDL入门例程。3个源程序。好好练习啊
Full adder. Introduction to VHDL routines. 3 source. Ah good practice (2013-05-14, VHDL, 4KB, 下载2次)
半加器的设计代码，和引脚的普通设置，有很多的功能有待研究！
succeful is good (2012-11-01, VHDL, 246KB, 下载3次)
半加器 东北大学秦皇岛分校 电子设计自动化 实验
Half adder Northeastern University at Qinhuangdao electronic design automation experiment (2012-06-27, VHDL, 20KB, 下载3次)
全加器 东北大学秦皇岛分校 电子设计自动化 实验
Full adder Northeastern University at Qinhuangdao electronic design automation experiment (2012-06-27, VHDL, 24KB, 下载3次)
基于VHDL语言的简单CPU，实现简单的加、减、乘
VHDL language based on the simple CPU, to achieve a simple addition, subtraction, multiplication (2012-05-11, VHDL, 1KB, 下载4次)
采用VHDL语言编写的半加器程序，希望对大家有用。
VHDL language using the half adder program, we hope to be useful. (2011-03-07, VHDL, 2KB, 下载3次)
用VHDL写的4位全加器,5.1版本编写的
Use VHDL to write four full adder, 5.1 version of the written (2010-08-10, VHDL, 130KB, 下载8次)
本代码实现了全加器的功能，可供初学者学习
This code implements a full adder functions, for beginners to learn (2009-09-22, VHDL, 3KB, 下载3次)
实现0-9999动态计数，每一秒钟计数加一，在xilinx XC35250上已经调通实现
dynamic display from 0 to 9999. (2009-08-07, VHDL, 437KB, 下载3次)
介绍用FPGA设计实现MIL-STD1553B部接口中的曼彻斯特码编解码器
presentation FPGA Design MIL-STD1553B Ministry interface Manchester encoding and decoding (2007-01-15, Others, 94KB, 下载68次)