里斯本Tecnico Digital System Design课程VHDL代码，
VHDL code for the course Digital System Design @ Técnico Lisboa, (2023-10-17, VHDL, 0KB, 下载0次)
锡林克斯深度学习IP，
Xilinx Deep Learning IP, (2021-05-10, VHDL, 0KB, 下载0次)
简单有效的曼彻斯特解码模块，工程验证可用
Simple and effective Manchester decoding module (2020-09-27, VHDL, 2KB, 下载2次)
用verilog寫成的ALU，有簡易的加減乘除、shifting、logic gate等功能。
Written by verilog ALU, there is a simple addition, subtraction, shifting, logic gate functions. (2016-12-03, VHDL, 236KB, 下载1次)
研究信道噪声对M-ary QAM的影响，适合数字通讯从业者
Effect of channel noise on M-ary QAM in (2015-07-15, VHDL, 756KB, 下载4次)
8位全加器，Verilog硬件语言源代码。最基础的加法器。
8-bit carry-ripple adder， the basic adder。Achieved by verilog source code. (2014-04-15, VHDL, 10KB, 下载3次)
一个基于FPGA的四位全加器的小程序，输入两个二进制数并计算结果。
An FPGA-based four full adder applet, enter two binary numbers and calculations. (2014-01-13, VHDL, 138KB, 下载3次)
这个程序是带置位的同步可逆（加1或减1）5进制计数器
This procedure is reversible with synchronous set (plus one or minus one) 5 binary counter (2013-08-20, VHDL, 523KB, 下载3次)
原理图方式实现8位全加器，文件类型为gdf ，vhd 文件
8-bit full adder schematic way, the file type for the GDF vhd file (2013-05-15, VHDL, 82KB, 下载3次)
EDA实验报告 内含 交通灯 数字时钟 全加器 触发器 的 代码灯
The EDA lab report contains the code of the traffic lights digital clock full adder trigger light (2013-05-11, VHDL, 501KB, 下载2次)
经测试过的串口译码，很好用的，可以试试，不清楚的可以加我Q258903455
The tested com decoding, nice, can have a try, don t know to increase my Q258903455
(2012-11-28, VHDL, 8KB, 下载5次)
里面附有两个VHDL实验，分别是一位全加器和计数译码显示模块
Experiments with two VHDL which, respectively, a full adder and the counter display module decoding
(2011-06-11, VHDL, 260KB, 下载5次)
LILIXN赛灵斯自带的ISE使用说明书。还不错哈。
the introduction ISE for lilinx. (2010-12-05, VHDL, 598KB, 下载4次)
viterbi译码器的算法原理加原代码，代码是VHDL的，内容详细，全英文
（2，1，7）viterbi译码器 (2009-11-03, VHDL, 1626KB, 下载127次)
vhdl,无进位同步计数器，完成6进制加，输出6进制序列数
vhdl, non-binary synchronous counter to complete the six binary Canada, output 6, the number of binary sequences (2009-09-07, VHDL, 37KB, 下载6次)
一个DDS芯片AD9851的VERILOG程序，加74HC574锁存器！
A DDS chip AD9851' s VERILOG program, plus 74HC574 latch! (2009-08-25, VHDL, 1KB, 下载19次)
曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0，低→ 高的跳变表示为1。每个码元中间都要发生跳变，接收端可将此变化提取出来作为同步信号，使接收端的时钟与发送设备的时钟保持一致
Manchester coding techniques that use voltage changes in 0 and 1. Provisions in the middle of each symbol hopping happen. High → low hopping express 0, low → high jump for the express one. Symbol between each transition must happen, this change in the receiver can be extracted as a synchronization signal to the receiving end of the clock and send the equipment to maintain the same clock (2009-04-05, VHDL, 89KB, 下载133次)
32位全加器 在querters II 下面运行成功 仿真 验证均已成功
32-bit full adder at querters II following the success of simulation runs have been successful (2009-03-21, VHDL, 6KB, 下载7次)
8位全加器的VHDL描述，可用MAX+plusⅡ运行测试
8-bit full adder of the VHDL description，MAX+ plus Ⅱ can be used to run test (2009-02-27, VHDL, 1KB, 下载12次)
常用经典典型电路，如全加器，乘法器，如何减小资源
Commonly used classical typical circuit, such as the full adder, multiplier, how to reduce the resources (2008-06-13, VHDL, 4KB, 下载3次)