ATARI俄罗斯方块街机游戏的FPGA实现
FPGA implementation of ATARI s Tetris arcade game (2019-12-28, VHDL, 2362KB, 下载0次)
Xilinx FPGA莫尔斯码译码器的VHDL编程
Morse Code Decoder for Xilinx FPGA using VHDL programming (2019-02-01, VHDL, 1864KB, 下载0次)
基于VHDL硬件描述语言的布斯乘法器，包含测试文件
Booth Multiplier based on VHDL, testbench included (2020-05-30, VHDL, 506KB, 下载1次)
利用quartus9.0中verilog语言实现的四位全加器，亲测有效
Using quartus9.0 Verilog language to achieve the four bit full adder, pro test effective (2017-06-28, VHDL, 92KB, 下载2次)
FPGA的代码verilog语言编写，包括LED与按键验证，数据选择器，编码器，译码器半加器，全加器，适合初学者，已经在板子调试成功，板子是 睿智IV开发板。
FPGA code verilog language, including LED and key authentication, data selection, encoder, decoder and a half adder, full adder, suitable for beginners, it has been successful commissioning of the board, the board is wise IV development board. (2015-10-25, VHDL, 20585KB, 下载2次)
用VHDL写的全加器，移位寄存器，和计数器，并有文档说明，非常详细。
Using VHDL write full adder, shift registers, and counters, and is documented in great detail. (2015-08-07, VHDL, 135KB, 下载3次)
现代超大规模集成电路设计课件，普伦蒂斯霍尔出版社。
modern vlsi design (2015-02-08, VHDL, 3601KB, 下载4次)
VHDL简易交通灯程序，数码管显示。没加译码程序。可以行加上
Simple traffic light VHDL program, digital display. Did not increase the decoding process. You can add the line (2014-12-15, VHDL, 1KB, 下载3次)
一款简单的俄罗斯方块游戏，用Verilog编写源码，方便大家学习
A simple tetris game, written in Verilog source, convenient for everybody to learn (2014-11-13, VHDL, 4503KB, 下载80次)
全流水线1维8点DCT变换，用于JPEG编码，无乘法运算,verilog
Full-line one-dimensional 8-point DCT, for JPEG encoding, no multiplication (2014-01-19, VHDL, 2KB, 下载4次)
16位二进制全加器，带最高位的进位，主要用QUARTUS仿真工具实现
16-bit binary full adder (2013-11-01, VHDL, 1KB, 下载2次)
简单的流水灯 比较简单 适合新手学习 没什么难度 类似38自加器
Simple light water is relatively simple for beginners to learn nothing from the adder 38 similar difficulty (2013-06-17, VHDL, 677KB, 下载2次)
eda实验报告，包括全加器、四选一数据选择器、交通灯。
eda lab reports, including full-adder, four elected a data selector, traffic lights. (2013-05-29, VHDL, 68KB, 下载5次)
这是一个成功的半加器VHDL源代码，已在DH－33001开发板上调试成功。
This is a successful half-adder VHDL source code, in the DH-33001 development board debugging. (2012-05-06, VHDL, 33KB, 下载4次)
這是半加器的代碼，希望對大家有些用，不足之處請見諒
This is a half adder code, we want to use some, please forgive the inadequacies (2011-09-21, VHDL, 172KB, 下载4次)
是十六位乘加器的VHDL语言描述。是我的课程设计。很好用。成绩是优秀
Is a sixteen by adder VHDL language description. My course design. Good use. Performance is excellent (2011-06-14, VHDL, 2150KB, 下载14次)
利用HDL语言编写的半加器，已经通过本人仿真验证，对于初学都很有帮助。
Written by HDL half adder, has passed my simulation, are very helpful for beginners. (2011-06-10, VHDL, 218KB, 下载4次)
自己做的信道编译码，（4，7）汉明码的加错解错源代码
Do their own channel coding, (4,7) Hamming code plus misconception wrong source (2010-04-26, VHDL, 3KB, 下载30次)
一位全加器，VERILOG实现，包括测试文件，测试可用，欢迎下载，共同学习
A full adder, VERILOG implementation, including test papers, test available, please download, a common study (2009-03-30, VHDL, 1KB, 下载2次)
四人抢答器设计,具有超前抢答显示报警，20秒倒计时超时抢答报警及加分、减分等功能
Answer four design, with advance Answer show alarm, countdown to 20 seconds of overtime Answer alarm and extra points, reducing the classification function (2008-12-21, VHDL, 2KB, 下载24次)