俄罗斯方块游戏的FPGA Verilog实现
Verilog implementation of Tetris game for FPGA (2024-02-08, Verilog, 0KB, 下载0次)
SystemVerilog设计使用DE10 Lite FPGA开发板上的加速度计
SystemVerilog design to use the accelerometer on the DE10-Lite FPGA Development Board (2021-05-26, SystemVerilog, 16KB, 下载0次)
用C++软件实现俄罗斯方块FPGA图形化
Tetris FPGA graphical implementation with C++ software (2023-05-03, C, 21170KB, 下载0次)
巴斯3乒乓球比赛
BASYS 3 - PONG GAME (2017-05-05, SystemVerilog, 86KB, 下载0次)
使用Verilog语言编程实现用有限状态机实现序列检测、全加器、AD转换等功能
Sequence detection with finite state machine (2020-01-14, Verilog, 2KB, 下载1次)
qdr2的verilog源代码，莱蒂斯FPGA
qdr2 verilog LATTICE FPGA (2017-04-24, VHDL, 16KB, 下载3次)
在本实验中，用三个按键开关来表示 1 位全加器的三个输入（ Ai、 Bi、 Ci）；
用二个 LED 来表示 1 位全加器的二个输出（ Si， C）。通过输入不同的值来观察输
入的结果与 1 位全加器的真值表（表 1-1）是否一致。
In this experiment, three button switches to represent three input a full adder (Ai, Bi, Ci) two by two LED to indicate output a full adder (Si, C). By entering different values and observe the results entered a full-adder truth table (Table 1-1) are the same. (2016-12-27, VHDL, 273KB, 下载1次)
完成LED的自加功能，里面包含完整的说明和测试文件
Complete self-plus-function LED, which contains complete instructions and test files (2015-04-14, VHDL, 3140KB, 下载1次)
数字式秒表大实验的设计代码,并附加测试代码
Digital stopwatch big experiment design code and test code attached (2014-05-07, VHDL, 33KB, 下载8次)
加按键程序,有助于vhdl语言的初级学习!可以下载看看.
Plus key procedures, contribute to the VHDL language the primary learning! Can download to see. (2013-04-29, VHDL, 27KB, 下载3次)
基于quartusiI的8位傅立叶变换。verlog程序加仿真。
Based quartusiI eight Fourier transform. verlog program plus simulation. (2012-11-20, LISP, 21769KB, 下载8次)
四位全加器，是自己编写的，如有错误，请原谅
I have written four full adder, is subject to error, please forgive (2012-11-17, VHDL, 39KB, 下载3次)
通过调用被实例化的模块来实现四位全加器功能
Four full adder function is achieved by calling the module is instantiated (2012-11-08, VHDL, 1KB, 下载3次)
VHDL的加、减、乘、比较等基本运算的源代码
VHDL add, subtract, multiply, compare the source code of the basic operations (2012-09-04, VHDL, 41KB, 下载4次)
通过使用VHDL语言编写程序实验1位半加器的功能
Through the use of VHDL language programming experiment 1 and a half adder function (2012-02-28, VHDL, 103KB, 下载3次)
里边有一个半加器。、一个全加器、一个触发器和一个无符号4乘4的乘法器程序，可以完成4位无符号数相乘
Inside there is a half adder. , A full adder, a flip-flop, and an unsigned 4 by 4 multiplier process can be completed by multiplying the number of 4-bit unsigned (2011-06-04, VHDL, 3KB, 下载6次)
曼彻斯特编码的VHDL语言实现，可以用于RFID防碰撞编码的实现
Manchester encoding of the VHDL language, can be used for implementation of RFID anti-collision code (2011-05-12, VHDL, 1KB, 下载15次)
用硬件描述语言编写的8位全加器代码，很实用！
Using hardware description language preparation 8 bits QuanJia implement code, very useful!! (2011-01-21, VHDL, 1KB, 下载3次)
QuartusII编程设计一款基于FPDA/QuartusII的计算机部件,可以实现算术运算(加,减,自加1,自减1,乘法,除法)和逻辑运算(与,或,非)等功能!
Based on a QuartusII Programming FPDA/QuartusII the computer components can be achieved Arithmetic (add, subtract, from plus 1, since the minus 1, multiplication, division) and logical operators (and, or, non-) and other functions! (2009-07-20, VHDL, 1989KB, 下载2次)
VHDL图形文件实现的4位全加器，希望对大家有用！
VHDL graphics files to achieve four full adder, in the hope that useful! (2009-06-24, VHDL, 148KB, 下载2次)