[VHDL/FPGA/Verilog] ASIC-FPGA-tetris
用于俄罗斯方块游戏的FPGA实现。
a FPGA implementation for tetris game. (2016-06-18, Verilog, 2156KB, 下载0次)
[VHDL/FPGA/Verilog] Tang-Nano_Tetris
唐纳米FPGA上的俄罗斯方块
Tetris on Tang-Nano FPGA (2022-01-04, GLSL, 1091KB, 下载0次)
[VHDL/FPGA/Verilog] vhdl-stopwatch
基于hdl的斯巴达板简易秒表
simple stopwatch using hdl for spartan board (2018-06-18, HTML, 302KB, 下载0次)
[VHDL/FPGA/Verilog] src
32位全加器设计，插入流水线，实现各数据同步
Design of 32-bit full adder, insert pipeline to realize data synchronization (2019-05-19, Verilog, 4KB, 下载1次)
[VHDL/FPGA/Verilog] m60v20161109
实现两位数从0到100的计时，每一秒加一。
The timing of two digits from 0 to 99 (2018-07-09, Quartus II, 268KB, 下载1次)
[VHDL/FPGA/Verilog] 2.adder
基于VHDL的全加器时间延迟分析，分析基本器件的传输延迟和惯性延迟
the analysis of timing delay of full adder in VHDL (2015-05-03, VHDL, 135KB, 下载2次)
[VHDL/FPGA/Verilog] FA
使用VERILOG實現全加器的設計,並附上TB供測試
Use VERILOG achieve full adder design, together with a test for TB (2014-07-07, VHDL, 1KB, 下载2次)
[VHDL/FPGA/Verilog] add4
方便扩展学习的四位全加器；用VHDL语言描述实现，是初学者一个不错的学习历程。。。完整可运行工程喔
4 bits adder (2013-12-04, VHDL, 238KB, 下载2次)
[VHDL/FPGA/Verilog] lcd
LCD1602的显示程序、加时钟、闹钟。等功能
LCD1602 display program, plus clock, alarm clock. Other functions (2013-07-12, Visual C++, 66KB, 下载5次)
[VHDL/FPGA/Verilog] fadder8
基于VHDL语言，编写一个32位全加器文件，可直接编译
Based on VHDL language, write a 32-bit full adder files can be directly compile (2011-12-28, VHDL, 486KB, 下载5次)
[VHDL/FPGA/Verilog] Experiment02
FPGA低级建模试验二流水灯加闪烁等，通过板级调试
FPGA test two low-level flow modeling lamp, flash, etc., by board-level debugging (2011-10-28, VHDL, 118KB, 下载3次)
[VHDL/FPGA/Verilog] AdderE-modelSim
全加器ModelSim工程，modelsim的仿真模型，在quartus下可运行
Full adder ModelSim project, modelsim simulation model can be run under the quartus (2011-10-05, VHDL, 187KB, 下载8次)
[VHDL/FPGA/Verilog] full_adder
通过运用quartusii运用vhdl语言描述一个全加器的设计程序
Vhdl language through the use of quartusii used to describe a full adder design process (2010-11-05, VHDL, 165KB, 下载5次)
[VHDL/FPGA/Verilog] chap3
全加器和记数器的测试文件，可直接用于modsim测试
Full adder and counter test documents, can be used directly in testing modsim (2009-03-20, VHDL, 5KB, 下载3次)
[VHDL/FPGA/Verilog] add_eight
用VHDL写的一个8位全加器的实验程序,供新手参考
Use VHDL to write an 8-bit full adder of the experimental procedures (2009-02-10, VHDL, 58KB, 下载2次)
[VHDL/FPGA/Verilog] Full_Adder
用VERILOG语言实现了全加器,可综合可仿真通过
Verilog language used to achieve the full adder can be integrated to simulation through (2008-06-01, VHDL, 70KB, 下载3次)
[VHDL/FPGA/Verilog] Project_Navigator_Demo
双向控制全加器的VHDL实现 内含ISE工程文件
Bi-directional control of the full adder VHDL realize intron ISE project file (2008-05-12, VHDL, 107KB, 下载5次)
[VHDL/FPGA/Verilog] reg_add
在quartus中仿真通过的移位加程序的vhdl代码
In the Quartus simulation procedures adopted by the transposition of the VHDL code (2008-01-08, Others, 511KB, 下载5次)
[VHDL/FPGA/Verilog] c8051lcd
c8051 LCD源程序，非常经典！推荐加经典
c8051 LCD source, the very classic! Suggest increase classic (2007-06-20, C/C++, 9KB, 下载34次)
[VHDL/FPGA/Verilog] jiafaqi
实现四位加法器的VHDL代码，里面含有全加器的代码
achieve four Adder VHDL code, which contains the full adder code (2006-10-25, Others, 1KB, 下载2次)