[工具库] Direct-mapped-Associative-mapped-cache-controller
直接映射和4路集关联映射高速缓存加高速缓存的VHDL代码，
VHDL code for direct-mapped and 4 way set associative-mapped cache plus cache memory, (2022-05-15, VHDL, 0KB, 下载0次)
[VHDL/FPGA/Verilog] 1
用VHDL语言设计全加器的设计方法，使用元件例化的方法设计多位加法器
VHDL language design full adder design method using component instantiation approach to design multi-bit adder (2016-03-21, VHDL, 1KB, 下载1次)
[VHDL/FPGA/Verilog] fulladder
关于全加器的VHDL设计文件，已做好的quartusII软件编程文件，直接下载就可以打开
About full adder VHDL design documents, quartusII software programming files have been prepared directly download can open
(2015-11-20, VHDL, 90KB, 下载1次)
[VHDL/FPGA/Verilog] jiafaqi
本实验中，我们将设计一个能进行加运算的8位（包括符号位）运算电路
In this experiment, we will design a can add operation 8 (including the sign bit) arithmetic circuit (2015-01-15, VHDL, 306KB, 下载1次)
[VHDL/FPGA/Verilog] total_adder
使用quarters编写的加法器以及全加器代码，包括整个工程的所有文件
Adder and a full adder using quarters written code, including all of the files of the entire project (2013-01-02, VHDL, 122KB, 下载2次)
[VHDL/FPGA/Verilog] uart
基于verilogHDL实现的UART收发，带FIFO缓存。
UART transceiver, with a FIFO buffer. (2012-12-30, VHDL, 324KB, 下载13次)
[VHDL/FPGA/Verilog] ALU_4bit
4位ALU,有两个4位输入，4位输出实现逻辑运算和算术运算，逻辑与或非，加1，减1等等功能
4 ALU, logical and arithmetic operations (2012-11-18, VHDL, 38KB, 下载14次)
[VHDL/FPGA/Verilog] Verilog
基于verilog HDL编写的各种实例。。里面记载了计数器，全加器，等等的代码。
Based on various examples written in verilog HDL. . Recording the counter, full adder, and so the code. (2011-11-18, VHDL, 242KB, 下载5次)
[VHDL/FPGA/Verilog] ADDER
verilog DHL编写的一位全加器，编译通过。稍作修改便可编程任意位加法器。
verilog DHL write a full adder, compiled by. Slight modifications can be programmed any adder. (2011-11-04, VHDL, 56KB, 下载5次)
[加密解密] Improved-Montgomery-algorithm-
改进的基2 Montgomery算法，解决了大素数的加解密运算问题
Improved base 2 Montgomery algorithm to solve the encryption and decryption of large prime numbers computing problems
(2011-10-19, VHDL, 3KB, 下载44次)
[VHDL/FPGA/Verilog] verilog-example
4位并行乘法器 4位超前加法器 ALU 计数器 滤波器 全加器 序列检测器 移位器
failed to translate (2011-07-12, VHDL, 6KB, 下载29次)
[VHDL/FPGA/Verilog] UART
用VHDL语言编程实现UART，8位数据位，校验位自己可以加！LIBERO仿真正确！
VHDL language programming with UART, 8 data bits, parity bit that they can add! LIBERO simulation correctly! (2011-05-01, VHDL, 14KB, 下载6次)
[VHDL/FPGA/Verilog] Full_adder
VHDL新手入门：全加器的实现及仿真，输入量为两个不同频时钟
VHDL Getting Started: full adder implementation and simulation, input clock frequency for the two different (2011-02-11, VHDL, 4KB, 下载2次)
[VHDL/FPGA/Verilog] vhdl_123
几个简单的vhdl程序。包括加法器，减法器，乘除法等等。
A few simple vhdl program. Including the adder, subtractor, multiplication and division and so on. (2010-11-02, VHDL, 4288KB, 下载21次)
[VHDL/FPGA/Verilog] Verilog
各类verilog源代码
计数器，全加器，串行快等。
All verilog source code counter, adder, serial quick. (2010-05-11, VHDL, 21KB, 下载21次)
[VHDL/FPGA/Verilog] half_divide
提供一种分频系数为整数加0.5的分频方法，并在Q2中验证
Provide a frequency division factor of the sub-integer frequency increase of 0.5 methods, and verify in Q2 (2010-04-18, VHDL, 1KB, 下载3次)
[Windows编程] counter_5_reversible
带置位的同步可逆（加1或减1）5进制计数器。
Reversible synchronous with the set (plus one or minus 1) 5 binary counter. (2009-08-31, VHDL, 321KB, 下载6次)
[VHDL/FPGA/Verilog] 65536
（1） 计数器的输入为RST（复位），EN（使能），CLK（时钟），U_D（up_down加/减选择）；输出为COUT（进位/借位输出），CQ（3：1）（数值输出）；
范围65536。
failed to translate (2009-05-16, VHDL, 57KB, 下载3次)
[单片机开发] DEMO3_KX8051_GPS_FTEST_2C5
此示例是8051核加频率计的联合设计,带有8051IP核资料
This example is the 8051 nuclear increase the frequency of joint design, with the nuclear information 8051IP (2009-04-10, VHDL, 464KB, 下载11次)
[VHDL/FPGA/Verilog] Electronic-Design-Automation-Vhdl
各种计数器，编码器，全加器等元件的VHDL语言描述
A variety of counters, encoders, such as full-adder components described in VHDL language (2008-12-17, VHDL, 14KB, 下载6次)