通过spi实现加速度计adxl357读取xyz三轴方向的加速度值
Accelerometers adxl357 read the acceleration value of XYZ three-axis direction through SPI (2020-03-06, VHDL, 5KB, 下载14次)
实现四连体数码管循环进位计数功能，每秒数字加1
Realizing the counting function of four continuous digital tubes (2018-08-06, VHDL, 2306KB, 下载0次)
各种密码算法的FPGA实现情况
1.AES算法FPGA实现分析
2.DES加密算法的高速FPGA实现
3.RSA加解密运算的FPGA硬件实现研究
FPGA implementation of various cryptographic algorithms (2018-04-22, VHDL, 17491KB, 下载45次)
基于ARM9和FPGA远程动态重构加解密研究_汪凯
Arm9-based remote and FPGA dynamic reconfiguration encryption research _ ja.in vivo magnetic resonance spectroscopy (2016-03-29, Visual C++, 5326KB, 下载1次)
矩阵键盘扫描以及数码管自动加一计数显示，适合初学者参考
Matrix keyboard scanning and automatically add a digital counter display, suitable for beginners reference (2015-10-16, VHDL, 112KB, 下载1次)
基于hdl的ofdm基带处理器发射机的设计与实现
包括 工作时钟 主控单元 导频插入 长短训练序列生成 data符号调制 循环前缀与加窗处理 IFFT/FFT 信道编码 扰码模块等
Hdl of ofdm transmitter baseband processor based design and implementation including work clock master unit pilot insertion length of the training sequence generated data symbol modulated cyclic prefix and windowing IFFT/FFT channel coding scrambling module, (2015-05-04, VHDL, 2538KB, 下载28次)
一个八位加法器，利用四个全加器组成，并兼有溢出提示功能
An eight adder using four full adder composed, and both spill prompts (2014-06-15, VHDL, 1KB, 下载2次)
verilog编写的可综合的加减法器 速度较快
verilog written on subtraction can be integrated faster (2013-12-08, VHDL, 176KB, 下载5次)
一位全加器的VHDL程序，上学时实验用的，很简单的，初学者可以看看
A full adder VHDL program, school experiment, very simple, beginners can look (2013-11-13, VHDL, 12KB, 下载2次)
成功接收艾法斯产品lvds信号的verilog程序，网上介绍比较少，希望有所帮助
Aeroflex products successfully received lvds signal verilog program, online presentation is relatively small, I hope to help (2013-09-13, VHDL, 8831KB, 下载10次)
2ASK的调制方式仿真，并叠加了高斯白噪声
2ASK modulation simulation, and superimposed a Gaussian white noise (2013-07-22, matlab, 59KB, 下载9次)
低通和高通分别作卷积的方法。用巴特沃斯滤波器构造数字二分频器。
Low-pass and high-pass respectively, for convolution approach. Digital Butterworth filter structure with two dividers. (2013-06-27, Others, 1KB, 下载5次)
曼彻斯特编码解码的代码，在网上找到的。因为毕设需要找到的，特此分享。
Manchester encoding and decoding the code found on the Internet. Need to find the complete set, is hereby share. (2012-06-05, VHDL, 1KB, 下载13次)
這是全加器,名字為fulladd4bit.rar,功能為四位元的加法。
This is the full adder, the name of fulladd4bit.rar function is the addition of four bits. (2012-04-17, VHDL, 1KB, 下载3次)
基于Verilog的7960实现。主要实现曼彻斯特的编解码。采用的倍频采样的方法。
Based on the 7960 Verilog implementation. Main achieved Manchester encoding and decoding. Frequency sampling method used. (2011-03-24, VHDL, 686KB, 下载19次)
基于VHDL语言编写的俄罗斯方块游戏，由VGA接口和电脑显示器显示，用PS2键盘操作控制。
Written in VHDL-based Tetris game, by the VGA interface and a computer display, with a PS2 keyboard control. (2010-09-06, VHDL, 3760KB, 下载75次)
AES 128bit数据,128bit密钥加解密的verilog语言实现
AES 128bit data, 128bit key encryption and decryption of the verilog language implementation (2010-01-08, VHDL, 78KB, 下载312次)
一维DCT变换的Verilog HDL源程序，在ISE中已经通过编译，可以参考里面的文档。
One-dimensional DCT transform Verilog HDL source code, in the ISE has been through the compilation, you can refer to inside the document. (2009-11-12, VHDL, 412KB, 下载41次)
2维DCt源码，可以实现8乘8点数据的2维DCT变换
2-D DCT-source, you can realize 8 x 8 data 2-D DCT transform (2008-05-15, VHDL, 5KB, 下载188次)
数据选择器，半加器，3-8译码器vhd源代码。是最近学校的实验内容。我要成会员，所以都发上来供大家参考。
data selection, half-adder ,3-8 decoder vhd source code. Recent experimental schools content. I want to become members and therefore has made onto for reference. (2005-12-11, TEXT, 11KB, 下载236次)