一个用于测试SPI加速度计测量和活动事件的不同实现的小型FPGA项目
A small FPGA project of different implementations for testing Measurement and Activity Events of a SPI accelerometer (2023-02-26, VHDL, 108315KB, 下载0次)
基于FPGA系列AX516芯片加OV7670摄像头的VGA模式识别程序
VGA pattern recognition program based on FPGA series AX516 chip plus OV7670 camera (2018-11-02, VHDL, 3775KB, 下载5次)
Xilinx 关于PCIE读写控制的官方例程。
Xilinx PCIE Demo (2016-10-21, VHDL, 13345KB, 下载42次)
此程序是FPGA 中用VHDL语言来实现半加器的功能，对于初学者很有参考价值。
This program is FPGA using VHDL language to achieve a half-adder function, a good reference for beginners. (2016-07-27, VHDL, 2KB, 下载1次)
例化语句生成的四位全加器代码，写在word里了，也有MODELSIM测试代码
Four cases of full adder codes generated by the statement, written in the word again, and there MODELSIM test code (2016-04-14, VHDL, 9KB, 下载1次)
卷积
严格遵守时序的一维卷积运算，用testbench测试了
convolution
write a VHDL file to compute one-dimensional convolution
latency 14 (2016-04-08, VHDL, 21620KB, 下载8次)
自己写的rc4加解密算法部分的verilog代码，可综合，供大家参考
Write your own encryption algorithm verilog codes rc4 section can be integrated, for your reference (2016-02-16, VHDL, 2KB, 下载19次)
使用特权EP1C的开发板，实现数码相框加灰度化功能，用verilog编程。
Privileged EP1C development board to achieve digital photo frame features plus gray, with verilog programming. (2015-01-30, VHDL, 10194KB, 下载4次)
能够使用4个按键，实现调时。一个选择，一个取消，一个加时间，一个减时间。
Four keys to use to achieve the transfer. A selection, a cancel an add time, a reduced time. (2014-05-15, VHDL, 1819KB, 下载4次)
计算器的verilog语言程序代码。能实现加、减、乘、除运算。
verilog language of counter。it can achiev plus o, minus, multiplication and addition operations (2013-09-29, VHDL, 21KB, 下载6次)
这个程序可以实现用图形输入方式，实现一个4位二进制全加器。
This procedure can be achieved using graphical input, to achieve a 4-bit binary full adder. (2013-08-20, VHDL, 568KB, 下载3次)
8位相等比较器，布斯乘法器，以为寄存器的VHDL实现
Eight for phase comparator, Booth multiplier, that registers of VHDL (2013-07-23, VHDL, 2KB, 下载1次)
光端机发送端ad飒飒fag阿斯达四方公司的
Optical transmitter ad sough fag Asda' s Quartet (2013-07-01, VHDL, 397KB, 下载9次)
verilog—Manchester 极为简单的曼彻斯特编解码 verilog实现 分为编码和解码两个部分
通过自己测试 同步异步均正常收发
extremely simple verilog-Manchester Manchester codec verilog achieve synchronization through their own test is divided into two parts of the encoding and decoding Asynchronous were normal transceiver (2013-03-05, VHDL, 1KB, 下载22次)
布斯乘法器 Booth Multiplier VHDL Code
Booth Multiplier VHDL Code (2012-12-27, VHDL, 5KB, 下载13次)
基verilog 布斯乘法器
4位位宽，本人不才，仅做参考
Booth multiplier based verilog (2010-08-12, VHDL, 1KB, 下载5次)
介绍利用XILINX spartan-3e 开发平台开发俄罗斯方块游戏，语言为VHDL
Introduced using XILINX spartan-3e Tetris game development platform, language VHDL (2010-05-20, VHDL, 193KB, 下载204次)
基于FPGA的曼彻斯编码器和译码器的实现源代码
the mancheshi decoder and encoder based on FPGA (2010-03-29, VHDL, 182KB, 下载6次)
用VHDL语言完成十秒倒计时电路以及四人抢答加分的系统
VHDL language with the completion of 10 seconds countdown circuit and four extra points to answer in the system (2010-03-19, VHDL, 352KB, 下载5次)
卷积码的解码所用到的加比选模块 很有用 可直接引用
Decoding convolutional codes by using the plus selection module can be directly useful to quote (2008-09-12, VHDL, 2KB, 下载15次)