[VHDL/FPGA/Verilog] FPGA-based-Morse-Code-decoder
基于FPGA的莫尔斯码解码器
FPGA based Morse Code decoder (2024-04-18, Verilog, 0KB, 下载0次)
[VHDL/FPGA/Verilog] cr-labs
阿维罗大学可重构计算课程实验室
Labs of the Reconfigurable Computing course, University of Aveiro (2020-06-02, VHDL, 475675KB, 下载0次)
[VHDL/FPGA/Verilog] 丁哲琴201701130704董红芳201824101404
就是一个用maxplus2做的4位全加器啦
It's a four bit full adder made of maxplus 2 (2020-07-02, HTML, 178KB, 下载0次)
[VHDL/FPGA/Verilog] spi_ctrl_demo
使用vhdl实现spi读取adxl357三轴方向的加速度计值
Using VHDL to realize SPI to read the accelerometer value in three-axis direction of adxl357 (2020-03-06, VHDL, 2KB, 下载4次)
[VHDL/FPGA/Verilog] half_adder_VHDLproject
常用的VHDL模块，适合VHDL入门者，本系列一共包含六个VHDL模块，本文件是半加器模块
1.算术逻辑单元（alu_1706）,实现算术逻辑运算
2.CPU寄存器组（cpu_register），实现四个通用寄存器（具有读写功能），一个PC寄存器（清零，置数，加一计数，减一计数，工作使能）。
3.全加器（full_adder）
4.半加器（half_adder）
5.3-8译码器（mutex_3to8）
6.计算机运算器（S6）实现运算器相关功能
VHDL modules commonly used for VHDL beginners, this series contains a total of six VHDL module, arithmetic logic unit (alu_1706), implement arithmetic and logic
2.CPU register set (cpu_register), to realize the four general-purpose registers (read and write functions), a PC register (cleared, set the number, plus one count minus one count, work enabled).
3. The full adder (full_adder)
4. The half-adder (half_adder)
5.3-8 decoder (mutex_3to8)
6. Computer operator (S6) to achieve operator-related functions (2016-05-24, VHDL, 1452KB, 下载1次)
[VHDL/FPGA/Verilog] full_adder_VHDLproject
常用的VHDL模块，适合VHDL入门者，本系列一共包含六个VHDL模块，本文件是全加器模块
1.算术逻辑单元（alu_1706）,实现算术逻辑运算
2.CPU寄存器组（cpu_register），实现四个通用寄存器（具有读写功能），一个PC寄存器（清零，置数，加一计数，减一计数，工作使能）。
3.全加器（full_adder）
4.半加器（half_adder）
5.3-8译码器（mutex_3to8）
6.计算机运算器（S6）实现运算器相关功能
VHDL modules commonly used for VHDL beginners, this series contains a total of six VHDL module, arithmetic logic unit (alu_1706), implement arithmetic and logic
2.CPU register set (cpu_register), to realize the four general-purpose registers (read and write functions), a PC register (cleared, set the number, plus one count minus one count, work enabled).
3. The full adder (full_adder)
4. The half-adder (half_adder)
5.3-8 decoder (mutex_3to8)
6. Computer operator (S6) to achieve operator-related functions (2016-05-24, VHDL, 1642KB, 下载1次)
[VHDL/FPGA/Verilog] eluosi_game
使用Quartus II 9.1完成俄罗斯方块游戏，只要使用有VGA和键盘接口的FPGA开发板就行实现。操作简单，使用的是VHDL和Verilog语言
Use the Quartus II 9.1 to complete the tetris game, as long as you use a VGA and keyboard interface implementation of FPGA development board. The operation is simple, the use of VHDL and the Verilog language (2016-02-17, VHDL, 2126KB, 下载26次)
[VHDL/FPGA/Verilog] NOIS-II_AES
基于NOIS II的AES加解密系统 完整的工程文件
NOIS II-based AES encryption and decryption of a complete project file system (2013-05-26, VHDL, 6569KB, 下载9次)
[VHDL/FPGA/Verilog] ssb
ssb的调制与解调，包括信号的产生、乘法器、加噪、BPF、解调等部分。
ssb modulation and demodulation, signal generation, multiplier, adding noise, BPF, demodulation section. (2013-04-11, matlab, 1KB, 下载5次)
[VHDL/FPGA/Verilog] Russiafont
开发手机，led显示屏等经常需要俄罗斯字体库，这个是标准俄罗斯字体库，ttf格式的。
The development of mobile phones, led display often need the the Russian font library, this is the standard Russian font library, ttf format. (2012-12-17, Others, 17KB, 下载6次)
[VHDL/FPGA/Verilog] VHDLAC97
using VHDL language, 是一个用AC97 控制LM4550的系统，可以real-time读听，如果需要录音功能可以直接加一个BRam
VHDL real-time writing-reading system (2012-11-12, VHDL, 2062KB, 下载6次)
[VHDL/FPGA/Verilog] alu
一个简单的算术逻辑运算模块的Verilog代码，可进行加、减、自增、自减，比较大小等运算
alu module (2012-09-13, VHDL, 1KB, 下载5次)
[VHDL/FPGA/Verilog] 4addr
用verilog 语言编写的4位全加器，还是入门基础必备.
Verilog language with 4bit full adder, or basic essential.also it s so important to learn verilog! (2012-04-22, VHDL, 1KB, 下载5次)
[VHDL/FPGA/Verilog] abmodp
加运算法中的求佘运算。abmodp.generate the control signals for calculating abmodp
Increase in the demand algorithm She operations. abmodp.generate the control signals for calculating abmodp (2011-10-05, VHDL, 2KB, 下载3次)
[VHDL/FPGA/Verilog] code
详细的解析加代码，是用VHDL写的编码器与解码器的简单应用
Plus detailed analysis code is written in VHDL encoder and decoder, a simple application (2011-05-08, VHDL, 97KB, 下载3次)
[VHDL/FPGA/Verilog] f_add
在QuartusII软件环境下，运用VHDL语言编写的全加器的实现，包含仿真波形
In quartusii software. use vhdl languages of the implementation of a simulation waveforms
(2011-01-07, VHDL, 167KB, 下载3次)
[VHDL/FPGA/Verilog] f_adder
1位全加器，原理图设计，包括波形仿真，和打包，可以直接在Quartus6..0中直接使用
A full adder, schematic design, including the waveform simulation (2010-04-22, VHDL, 149KB, 下载5次)
[VHDL/FPGA/Verilog] h_adder
一种半加器的算法，是基于VHDL软件仿真。请大家下载参考！
A full-adder algorithm is based on the VHDL software emulation. Please download the reference! (2009-09-15, VHDL, 10KB, 下载5次)
[VHDL/FPGA/Verilog] out
verilog语言编写的米勒解码的输出模块加仿真波形正确了
Miller verilog language decoder output waveform simulation module plus correct (2009-06-19, Others, 229KB, 下载29次)
[VHDL/FPGA/Verilog] key_scan
verilog 键盘扫描,数码管显示程序，没有加消抖
verilog keyboard scanning, digital tube display program, there is no increase in consumer Buffeting (2009-05-07, VHDL, 1KB, 下载27次)