FPGA俄罗斯方块游戏，不使用软硬核处理器
FPGA Tetris game without utilizing a soft hard-core processor (2020-12-05, VHDL, 25786KB, 下载0次)
通过VHDL语言编写的一位全加器程序，该程序是经过元件例化的方式实现
VHDL language through a full adder program, which is the result of component instantiation way to achieve (2016-07-18, VHDL, 318KB, 下载3次)
飞加器(Flying-Adder，FA)频率合成技术应运而生。它的结构原型是2000年时Liming Xiu提出的一个能在多种频率值之间较快切换的电路。
FLYING-ADDER DIRECT PERIOD
SYNTHESIS ARCHITECTURE (2016-04-14, VHDL, 4986KB, 下载3次)
CPU 5级流水线实现（加hazard处理与板级验证，板级验证带有按键消抖）
5-stage pipelined CPU (plus hazard dealing with board-level verification, board-level verification with key debounce) (2016-04-07, VHDL, 14KB, 下载6次)
STM32F103ZET6开发板原理图加pcB版 1141170704收集
stm32 de yuan li tu jia pcb wen jian you xu yao de ke yi can kao yi xia (2014-12-03, VHDL, 1874KB, 下载59次)
verilog实现的rsa加解密系统，包括大素数生成算法，包含测试文件。
rsa encryption system using verilog, including large prime number generation algorithms, including test file. (2014-06-28, VHDL, 1577KB, 下载54次)
FPGA上的一个全加器实例程序，通过测试，可以直接运行在fpga开发板上。
A full adder example on FPGA program, through the test, can be run directly on the FPGA development board. (2013-12-01, VHDL, 316KB, 下载3次)
流水灯加单位数码管
流水灯自动来回流动，单位数码管自动计数
Light water units plus digital tube light water flow back and forth the unit digital tube automatic counting (2013-05-13, VHDL, 8KB, 下载3次)
按键控制波形加数码管
通过按键控制多位数码管的显示以及波形的变化
Keys to control the waveform plus digital tube through the key control a number of digital tube display and waveform changes (2013-05-13, VHDL, 924KB, 下载2次)
可逆计数器
一个可逆的十进制计数器，控制端为1时加计数，为0时减计数
Decimal counter the reversible counter a reversible control end 1:00 plus count, count down for 0:00 (2012-09-03, VHDL, 213KB, 下载4次)
键盘去抖程序，额外的加一个延时判决来判定时钟到来时是信号的到来还是干扰的因素，达到了比较好的效果，与大家分享
a design for key jitter (2012-05-12, VHDL, 320KB, 下载4次)
一维DCT变换，使用Verilog ＨＤＬ语言实现。有ＳＹｎｐｌｉｆｙ编译脚本
One-dimensional DCT, using the Verilog HDL language to achieve. The SYnplify compiled script (2012-05-08, VHDL, 2KB, 下载10次)
用两个方法实现2位全加器，没有错误，仅供参考。
Can realize two eight bits of Numbers is equal, no error, for reference. With two method two QuanJia device without any error, only supplies the reference.
(2012-03-30, VHDL, 1KB, 下载3次)
半加器，可移植性很强，只需改变内部的数字，即可得到任意的加法器！
The counter, portability is very strong, only need to a change in the inside of the digital can get any counter!!!!!
(2011-08-09, VHDL, 1KB, 下载4次)
该代码主要是对，由一个功能控制键控制全加的计数以及全减的计数
The code key is right control key functions controlled by a count of all Canadian and the count full reduction (2010-11-09, VHDL, 274KB, 下载3次)
一些用verilog编写的小程序，有全加器，计数器，比较器VGA显示，键盘扫描等
Some small programs written using verilog have full adder, counter, comparator VGA display, keyboard scanning, etc. (2010-07-06, VHDL, 8696KB, 下载22次)
模十计数器，状态机，用状态机控制计数器，00为保持，01为加1计数，02为+2计数
module10
counter (2009-07-27, VHDL, 1KB, 下载5次)
全加器仿真程序. 大家可以参考下 ，本人检查无误。无毒。如有问题，请来信咨询。
Full adder simulation program. You can refer to, I check the accuracy. Non-toxic. If you have any questions, please contact us advice. (2009-05-26, VHDL, 1KB, 下载4次)
实现时钟功能，有计数，复位，调整时间，既秒加一功能等，添加了按键的功能。
The realization of the clock function, count, reset, adjust the time, both function-plus-one seconds, add the button functions. (2009-05-11, VHDL, 2KB, 下载4次)
时钟信号输入端，要求编制一个顶层文件，产生具有自动加一功能的地址加法器
Input clock signal, called for a top-level document, resulting in an automatic function of the address-plus-one adder (2008-06-01, VHDL, 259KB, 下载2次)