FPGA HDL莫尔斯码编码器
FPGA HDL MORSE CODE ENCODER (2024-05-11, Others, 0KB, 下载0次)
卡米尼奥·德·达多斯(Caminho de dados feito em verilog),
Caminho de dados feito em verilog, (2023-07-20, Verilog, 0KB, 下载0次)
2020锡林克斯暑期学校
2020 xilinx summer school (2020-08-13, Jupyter Notebook, 1824KB, 下载0次)
曼彻斯特小型实验计算机的VHDL实现。
VHDL Implementation of the Manchester Small Scale experiminetal Computer. (2015-10-05, VHDL, 2391KB, 下载0次)
流行视频游戏俄罗斯方块的Verilog实现。
A Verilog implementation of the popular video game Tetris. (2015-10-28, Verilog, 14KB, 下载0次)
FPGA基础代码,模10计数器,可实现加计数
FPGA code base mold 10 counters, counting can be achieved (2016-12-11, VHDL, 404KB, 下载2次)
加性高斯白噪声生成的VERILOG实现,包含所有的testbench文件。可直接使用
Additive white gaussian noise generated VERILOG realized, including all testbench files. Can be used directly (2016-12-06, VHDL, 866KB, 下载79次)
这是一个计数器,可以实现自加1操作的自动计数器。
this is a counter ,By Mika realization operational counter add 1. (2015-07-13, VHDL, 2928KB, 下载4次)
基于VHDL的4位加法器。
由4个一位全加器级联构成。
VHDL-based 4-bit adder.
One consists of four full adder cascade. (2014-03-30, VHDL, 1KB, 下载1次)
此程序是用VHDL语言描写的全加器程序,从顶层开始设计的
This procedure is described using VHDL full adder program, designed to start from the top (2013-12-25, VHDL, 98KB, 下载1次)
简单的三人表决、一位全加器、三八译码器的VHDL语言的实现
Three simple voting, a full adder, the three eight decoder ,use VHDL language
(2013-07-15, VHDL, 1KB, 下载2次)
在板子上全部实现。代码有:1.一位全加器;2.LED计数器;3.数码管显示0-9;4.60秒数码管计数显示;5.电子钟;6.SOPC;7.定时中断;8. TLV5618;9.按键计数
在板子上全部实现。代码有:1.一位全加器;2.LED计数器;3.数码管显示0-9;4.60秒数码管计数显示;5.电子钟;6.SOPC;7.定时中断;8. TLV5618;9.按键计数 (2013-05-08, VHDL, 21KB, 下载18次)
这个是用verilog语言写的一个全加器的程序
This is to use verilog language to write a full adder program
(2012-12-27, VHDL, 223KB, 下载3次)
1位全加器的VHDL设计,已经在试验箱上实验通过。
VHDL design of a full adder has been in the chamber on the experiment through. (2012-04-08, VHDL, 116KB, 下载5次)
2路视频数据加4路串行数据编解码,系统时钟30M
2-way video data plus 4-way serial data encoding and decoding, the system clock 30M (2011-09-14, VHDL, 405KB, 下载7次)
vhdl语言实现cpld功能,本程序包括全加器,触发器,交通灯程序,适用maxII软件调试。
include full_adder,plus,traffic (2009-07-15, VHDL, 658KB, 下载6次)
32位全加器 在querters II 下面运行成功 仿真 验证均已成功
32-bit full adder at querters II following the success of simulation runs have been successful (2009-03-21, VHDL, 6KB, 下载7次)
8位全加器的VHDL描述,可用MAX+plusⅡ运行测试
8-bit full adder of the VHDL description,MAX+ plus Ⅱ can be used to run test (2009-02-27, VHDL, 1KB, 下载12次)
这个程序是仿真计算加golay编码的bpsk的ber计算
This process is simulation plus Golay encoded BPSK ber of calculation (2007-04-10, matlab, 1KB, 下载40次)
用VHDL编写的8位全加器,数字分频器等程序
VHDL prepared by the eight All-Canadian, digital dividers procedures (2006-05-20, Others, 556KB, 下载26次)