里面是全加器的代码，共五种，分别用不同语句写的
There are five kinds of code in it, which are written in different sentences. (2017-12-31, VHDL, 1KB, 下载1次)
自己编写的半加器源代码，直接导入工程即可，请下载使用。
Written in their own half adder source code, you can directly import project, please download. (2015-09-14, VHDL, 241KB, 下载3次)
移位加乘法器的实现；移位加乘法器的流水线结构的实现。代码清晰明了。
multiply verilog RTL；pipelin multiply verilog RTL；good coding stytle (2015-09-12, VHDL, 2KB, 下载1次)
基于verilog语言的编写的全加器，基于verilog语言的编写的全加器
quanjiaqi (2015-08-30, VHDL, 1KB, 下载1次)
2位全加器，实现全加器的功能，有近位的加法，输出也有近位，还有testbench,进行验证，验证通过
Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output (2014-05-14, VHDL, 1KB, 下载4次)
曼彻斯特编解码 曼彻斯特编解码 (2013-01-17, VHDL, 195KB, 下载13次)
http://www.pudn.com/Download/item/id/2120126.html
4位全加器的verilog程序设计.......
Four full adder verilog programming ... (2012-08-13, VHDL, 4158KB, 下载3次)
16位的加法器，全加器，有效的利用了门电路用以实现全加器的进位
16 of the adder, full adder and effective use of the gate for the binary full adder (2012-07-12, VHDL, 1KB, 下载4次)
4位全加器7483和4位比较器7485实现一位8421BCD码全加器
Four full adder 7483, and four comparator 7485 a 8421BCD code full adder (2012-04-29, VHDL, 197KB, 下载13次)
8421BCD码全加器,这个是最简单的8421加法器，也是最基础的，初学者用来练习
adders for 8241BCD (2011-12-20, VHDL, 306KB, 下载4次)
数字系统设计及VHDL实践半加器与全加器源代码
half-adder and full-adder (2011-12-10, VHDL, 1KB, 下载2次)
在Quartus II中用VHDL语言编写的全加器与半加器程序，全加器是调用半加器来实现的。
In the Quartus II VHDL language using the full adder and half adder program, full-adder is called a half adder to achieve. (2011-07-03, VHDL, 180KB, 下载4次)
一位全加器,使用绘图方式,将2个半加器制成符号,供全加器调用,组合成全加器,方法简单易行,通过验证.
A full adder, using the drawing method will be made of two half adder symbol calls for the full adder, adder combination of sake, the method is simple and verified. (2010-10-18, VHDL, 184KB, 下载4次)
模拟了半加器和全加器的vhdl语言源码。
model half add and full add mechine vhdl code (2010-06-09, VHDL, 505KB, 下载7次)
曼彻斯特编码器与译码器 FPGA嵌入式项目开发
mancodec fpga (2009-12-23, VHDL, 182KB, 下载127次)
应用一位全加器的VHDL语言，创建一位全加器符号，用原理图完成四位全加器
Application of a full adder VHDL language, to create a full-adder symbol, with the principle of the completion of four full adder diagram (2009-11-29, VHDL, 146KB, 下载15次)
利用两个半加器来组成的全加器，是简单的vhdl语言入门
The use of two and a half adder to form the full adder is a simple entry-vhdl language (2009-04-09, VHDL, 1KB, 下载4次)
八位全加器，实现自动加法，哈哈哈，大家共享
hello (2009-03-26, VHDL, 204KB, 下载2次)
曼彻斯特编码源代码 基于VHDL语言的曼彻斯特编码程序
manchester encode (2009-03-04, VHDL, 1KB, 下载10次)
这是一个4位全加器，用一个1位半价做的一位全加，然后做成的四位半加。
This is a 4-bit full adder, a half-price with a make a full-adder, and then made four half adder. (2008-03-24, VHDL, 95KB, 下载129次)