Trabalho desenvolvido para a disciplina de Laboraório de Hardware特拉巴略·德森沃尔维多·帕拉阿·拉布拉托硬件实验室
Trabalho desenvolvido para a disciplina de Laboratório de Hardware (2023-11-19, VHDL, 0KB, 下载0次)
达特茅斯ENGS31最终项目：数字电子。与Sam Siaw合作。
Final Project for Dartmouth s ENGS 31: Digital Electronics. Working with Sam Siaw. (2021-06-07, VHDL, 48KB, 下载0次)
基于FPGA的俄罗斯方块游戏的裸金属纯硬件实现
A bare-metal pure hardware implementation of the Tetris game for FPGA (2017-04-25, VHDL, 23KB, 下载0次)
2位全加器的多种实现方法，有门级电路、组合电路、输入输出模型
3 different ways to build a 2-bit full adder,including gate-level model,carry-in and out ect. (2020-05-12, VHDL, 1KB, 下载0次)
fpga单片机通过数码管实现1S自加功能，时间通过计数器实现
The fpga single chip machine implements the 1S self-addition function through the digital tube, and the time is achieved through the counter (2017-05-26, VHDL, 1KB, 下载1次)
本程序实现简单的fifo传输，并没有加其他的功能，试用芯片xilinx，verilog语言编写
The program implements a simple fifo transmission, and no other added features, try chip xilinx, verilog language (2016-03-07, VHDL, 3689KB, 下载4次)
同步计数器，利用有限状态机完成,能够完成000-999的加计数以及减计数功能
Synchronous counter which using finite state machine and able to complete the 000-999 plus count as well as the count function. (2015-07-04, VHDL, 14KB, 下载4次)
北京邮电大学VHDL课程作业，基于xilince ISE试验箱开发的，可以做简单的半加器加法
Beijing University of Posts and VHDL course work, based xilince ISE chamber developed, can do simple addition of half-adder (2014-05-09, VHDL, 1671KB, 下载2次)
布斯乘法器，采用verilog语言实现 经过modelsim仿真
Booth multiplier using verilog language through modelsim simulation (2013-12-24, VHDL, 1KB, 下载17次)
FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。
One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board (2013-12-01, VHDL, 327KB, 下载3次)
不等长编码的设计，对莫尔斯电码的改进，用vhdl实现
Unequal-length coding design, Morse code improvements, using vhdl (2013-10-31, VHDL, 15334KB, 下载2次)
俄罗斯方块游戏。可改变游戏速度，实现了最简单的功能，包含分频、按键防抖，可在8*8点阵上显示。
Tetris game. You can change the speed of the game, the most simple functions contains divider button image stabilization, 8* 8 dot matrix display. (2013-04-14, VHDL, 2KB, 下载16次)
采用vhdl编程，能实现曼彻斯特编码，仿真结果经验证。
Vhdl programming, Manchester encoding, proven simulation results can be achieved. (2012-10-14, VHDL, 1KB, 下载23次)
极值点遍历算法，将n次一维极值点遍历结果比较，输出。
Traversal algorithm for extreme points, the n-th one-dimensional extreme points traverse the results of the output. (2012-05-17, VHDL, 9KB, 下载6次)
加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。若加数、被加数与低位的进位数为输入，而和数与进位为输出则为全加器。
The number of adder is produced and device. Addend and BeiJiaShu as input, and the device for output with binary for half a gal device. If BeiJiaShu and low addends, into digits for input, and and and carry for the output is for QuanJia device.
(2011-04-03, VHDL, 295KB, 下载4次)
1553曼彻斯特编码的verilog代码
1553 Manchester coding verilog code (2010-12-07, VHDL, 1KB, 下载41次)
二阶低通数字巴特沃斯滤波器设计（四路并行处理）
Second-order filter design (four parallel processing) (2010-05-17, VHDL, 1KB, 下载39次)
全加器的VHDL逻辑编程，外加两个全功能，这个过程有些简单，但可能有一些初学者的帮助。
Full adder VHDL logic programming, plus two full-function, this process some simple, but there may be some beginners help. (2010-03-13, VHDL, 1KB, 下载3次)
加法器和全加器参考程序，由VHDL代码编写。初学者可以看一看。内容无毒，下载请杀毒使用。
Adder reference procedures, prepared by the VHDL code. Beginners can take a look at. Content-free, download antivirus, please use. (2009-05-26, VHDL, 1KB, 下载48次)
时钟信号输入端，要求编制一个顶层文件，产生具有自动加一功能的地址加法器
Input clock signal, called for a top-level document, resulting in an automatic function of the address-plus-one adder (2008-06-01, VHDL, 282KB, 下载2次)