在SystemVerilog中使用Vivado开发的Zybo Z720 SOC FPGA的NES系统。丹顿·克莱恩（Danton Klein）和安东尼·斯特罗斯（Anthony Stross）。
An NES system for an Zybo Z720 SOC FPGA developed in SystemVerilog using Vivado. By Danton Klein and Anthony Stross. (2024-01-19, VHDL, 0KB, 下载0次)
里斯本Tecnico Digital System Design课程VHDL代码，
VHDL code for the course Digital System Design @ Técnico Lisboa, (2023-10-17, VHDL, 0KB, 下载0次)
一种基于FPGA器件的自振荡MEMS加速度计控制程序（Altera Cyclone）
A control program for the self-oscillating MEMS accelerometer based on a FPGA device (Altera Cyclone) (2021-04-03, C++, 2876KB, 下载0次)
用verilog寫成的ALU，有簡易的加減乘除、shifting、logic gate等功能。
Written by verilog ALU, there is a simple addition, subtraction, shifting, logic gate functions. (2016-12-03, VHDL, 236KB, 下载1次)
VHDL实现的贪吃蛇，碰到自己身体或规定范围壁障游戏结束，每吃3个点身体长度加1
VHDL Snake (2016-01-05, Others, 3KB, 下载2次)
8位全加器，Verilog硬件语言源代码。最基础的加法器。
8-bit carry-ripple adder， the basic adder。Achieved by verilog source code. (2014-04-15, VHDL, 10KB, 下载3次)
一个基于FPGA的四位全加器的小程序，输入两个二进制数并计算结果。
An FPGA-based four full adder applet, enter two binary numbers and calculations. (2014-01-13, VHDL, 138KB, 下载3次)
原理图方式实现8位全加器，文件类型为gdf ，vhd 文件
8-bit full adder schematic way, the file type for the GDF vhd file (2013-05-15, VHDL, 82KB, 下载3次)
设计滤波器（包括双线性变换法和直接法）巴特沃斯型的
Filter design (2012-12-26, matlab, 1KB, 下载2次)
经测试过的串口译码，很好用的，可以试试，不清楚的可以加我Q258903455
The tested com decoding, nice, can have a try, don t know to increase my Q258903455
(2012-11-28, VHDL, 8KB, 下载5次)
里面附有两个VHDL实验，分别是一位全加器和计数译码显示模块
Experiments with two VHDL which, respectively, a full adder and the counter display module decoding
(2011-06-11, VHDL, 260KB, 下载5次)
基于fpga 的航空总线设计资料 MIL_STD_1553B总线设计系统 曼彻斯特码的编码等等
Fpga-based design information MIL_STD_1553B air bus system bus design, etc. Manchester encoding (2011-04-26, VHDL, 46426KB, 下载45次)
LILIXN赛灵斯自带的ISE使用说明书。还不错哈。
the introduction ISE for lilinx. (2010-12-05, VHDL, 598KB, 下载4次)
基于SOPC实现的俄罗斯方块,用VGA来做显示，PS2键盘来控制
SOPC-based implementation of Tetris, to do with the VGA display, PS2 keyboard to control the (2010-11-03, VHDL, 12848KB, 下载48次)
每按下开关，计数器加1且通过发光二极管显示出来
Each switch is pressed, the counter increased by 1 and shown by light-emitting diode (2010-04-29, Visual C++, 34KB, 下载4次)
曼彻斯特编码技术用电压的变化表示0和1。规定在每个码元中间发生跳变。高→ 低的跳变表示0，低→ 高的跳变表示为1。每个码元中间都要发生跳变，接收端可将此变化提取出来作为同步信号，使接收端的时钟与发送设备的时钟保持一致
Manchester coding techniques that use voltage changes in 0 and 1. Provisions in the middle of each symbol hopping happen. High → low hopping express 0, low → high jump for the express one. Symbol between each transition must happen, this change in the receiver can be extracted as a synchronization signal to the receiving end of the clock and send the equipment to maintain the same clock (2009-04-05, VHDL, 89KB, 下载133次)
常用经典典型电路，如全加器，乘法器，如何减小资源
Commonly used classical typical circuit, such as the full adder, multiplier, how to reduce the resources (2008-06-13, VHDL, 4KB, 下载3次)
三位全加器的源代码，和测试代码，用Verilog HDL实现的！
The three full adder of the source code, and test code, using Verilog HDL to achieve! (2008-03-18, Others, 35KB, 下载11次)
是一個用verilog寫成的加法器電路,可把七個元件加起來
Is a written with Verilog adder circuit, can add up to seven components (2008-03-17, Windows_Unix, 84KB, 下载3次)
verilog语言中 testbencch编写-仿真工具综合工具使用-全加器实例讲解
Verilog language testbencch preparation- the use of simulation tools integrated tools- examples of full adder on the (2008-01-11, PDF, 185KB, 下载8次)