半加器的代码，以及ucf文件，仿真已过，可在basys2上运行
The code of the semi adder, as well as the UCF file, has passed the simulation and can be run on basys2 (2020-05-03, VHDL, 933KB, 下载0次)
这是一个半加器的编码，功能简单，编程简单
This is a half adder code, simple in function and programming (2020-03-19, VHDL, 1483KB, 下载0次)
一个简单的半加器，包括图形编辑方法，并已下载
A simple half adder, including graphics editing method, and has been downloaded (2018-03-14, VHDL, 158KB, 下载1次)
基于两个半加器和一个异或门组成的全加器（资料中波形图为半加器的时序仿真图）
Based on two half-adder and an exclusive-or gate full adder (profile picture shows a half adder waveform timing simulation diagram) (2016-08-30, VHDL, 61KB, 下载1次)
研究生课程 ： 一维DCT功能实现，以及测试。
From Graduate courses : one-dimensional DCT function implementation, and testing. (2014-07-08, VHDL, 78KB, 下载2次)
5位全加器，与4位全加器相比较对新手来说更能深刻的理解Verilog语言。
5 bit full adder, compared with a 4 bit full adder for the novice can be more profound understanding of Verilog language.
(2014-06-27, VHDL, 2744KB, 下载4次)
AES加解密Verilog HDL源代码，具体的算法参照相关书籍，里面含有testbench
AES encryption and decryption Verilog HDL source code, reference books specific algorithm, which contains testbench (2014-05-09, VHDL, 8KB, 下载19次)
verilog HDL编写的俄罗斯方块程序，包含游戏控制，得分统计，VGA，PS2键盘控制等模块
verilog HDL Tetris program, including game control, Won, VGA, PS2 keyboard control modules (2013-12-24, VHDL, 1903KB, 下载53次)
本代码包含四位全加器和四位全加器的测试平台。
The code contains four full adders and four full adder test platform. (2013-05-23, VHDL, 1KB, 下载3次)
科斯塔斯环环路滤波器的VHDL实现，仅供参考，同时有计算相关的VHDL实现代码。
Costas loop filter in VHDL, for reference only
And calculates the associated VHDL code.
(2012-07-20, VHDL, 3KB, 下载59次)
加法器、寄存器、半加器、译码器的硬件描述语言的描述
describe summator ，register，half adder,decoder with VHDL (2012-05-16, VHDL, 2KB, 下载3次)
利用verilog HDL实现的AES算法，在密码芯片加解密中显示出了突出的优越性
The reference-AES.V which has been uploaded is particularly useful for researchers who are dedicated to the password-chip researching. (2011-11-22, VHDL, 8787KB, 下载20次)
一个16位ALU设计，该ALU主要能实现算术运算(加、减、带进位加、带进位减、加1、减1、传输)、逻辑运算(与、或、非、异或、同或、逻辑左移、逻辑右移操作)。
16bitALU vrilog Code (2011-01-04, VHDL, 1KB, 下载11次)
用verilog在半加器的基础上实现了全加器，方法简单巧妙，对于FPGA入门学习很有帮助
In the half adder using verilog on the basis of a full adder, simple and clever, very helpful for the FPGA Starter (2010-12-21, VHDL, 267KB, 下载3次)
完成一维小波变换一级分解。此文件包含小波变换的mallat算法，经测试完全正确。
Completed a one-dimensional wavelet transform decomposition. This file contains the mallat wavelet transform algorithm, the test is correct. (2010-11-05, VHDL, 1522KB, 下载48次)
布斯公式求补码乘法的算法，用VHDL语言编写
booth algrithm, work out the 2 s complement mulitplier using VHDL (2010-04-26, VHDL, 1KB, 下载37次)
AES 加解密 代码, 有文档说明，testbench
AES encoding decoding source code in HDL (2009-06-23, VHDL, 228KB, 下载100次)
四位BOOTH乘法器 Booth算法(布斯算法),一个比较推荐的带符号乘法算法
Booth_mul4 (2009-06-07, VHDL, 152KB, 下载33次)
一个全加器的VHDL程序,经过编译和仿真.
A full adder of the VHDL program, after compiling and simulation. (2008-11-11, VHDL, 149KB, 下载62次)
半加器 或门 1位二进制全加器顶层设计描述
Half adder or a binary gate full adder top-level design description (2008-11-06, VHDL, 1KB, 下载5次)