fpga高维
fpga hiwi (2023-12-01, VHDL, 0KB, 下载0次)
这个工程是实现HDB3码的编码功能,可分别输入加V、加B以及最终的HDB3码
This project is to achieve HDB3 code encoding function (2013-12-17, VHDL, 5720KB, 下载8次)
实现des加密芯片的设计与实现，包括了源代码，加解密设计。
DES encryption chip design and implementation, including source code, encryption and decryption design. (2013-05-18, VHDL, 20KB, 下载1次)
一位全加器
一位全加器(FA)的逻辑表达式为：
S＝A⊕B⊕Cin；
Co＝AB＋BCin＋ACin。
其中A,B为要相加的数，Cin为进位输入；S为和，Co是进位输出；如果要实现多位加法可以进行级联，就是串起来使用；比如32位+32位，就需要32个全加器。
A full adder is a logical expression of the full adder (FA): S = A ⊕ B ⊕ Cin Co = AB+ BCin+ ACin. Wherein A, B for the number to be added, Cin for the carry bit input S is and, Co is the carry output if you want to achieve many of the adder can be cascaded is string together use instance 32+32 bit, you need 32 a full adder. (2013-01-24, VHDL, 97KB, 下载10次)
通过调用半加器模块，实现全加器设计，含测试代码，通过验证
By calling the module of the half adder full adder design, with test code, by verifying (2012-06-25, VHDL, 189KB, 下载3次)
一位半加器工程，用xilinx ISE设计，供初学者学习
A half adder project using xilinx the ISE design for beginners to learn (2012-06-24, VHDL, 117KB, 下载2次)
半加器设计。有用的实验操作报告。EDA有详细的操作步骤
Half adder design. Useful experimental operation report. Detailed steps in EDA (2012-05-23, VHDL, 635KB, 下载6次)
4位串联全加器的fpga实现，由4个一位全加器组成
Four series of fpga realizing the QuanJia by 4 a QuanJia emulators (2012-05-06, VHDL, 12KB, 下载3次)
全加器程序编写，用VHDL语言实现四位全加器的加法运算
Full adder programming, using VHDL language to achieve the addition of four full-adder operation (2011-12-13, VHDL, 24KB, 下载2次)
四位元全加器,為Verilog/VHDL構成的IP模組電路
4bit fulladder (2011-09-15, VHDL, 12KB, 下载5次)
由四位全加器通过元件例化语句设计成十六位的全加器
By four full adder component instantiated by statements designed 16 of the full adder (2010-07-27, VHDL, 518KB, 下载12次)
基于VHDL的曼彻斯特编解码的设计程序及仿真波形
Manchester code (2010-05-30, VHDL, 304KB, 下载47次)
半加器源代码，用VHDL语言编写有需要的可以看看
Half adder source code, using VHDL language need to look at (2010-05-12, VHDL, 119KB, 下载4次)
用vga显示俄罗斯方块基于fpga但是不是真正的游戏俄罗斯方块
Tetris with vga display based on the fpga, but not a true game Tetris (2010-02-02, VHDL, 2250KB, 下载64次)
用例化语句和case语句编写的全加器的VHDL描述。
Of statements were prepared using the full adder of the VHDL description. (2009-04-12, VHDL, 63KB, 下载4次)
全加器，半加器，或语句，三个建在一个文件中就可以用了
Full adder, half adder, or statement, three built in one file can be used (2009-03-27, VHDL, 1KB, 下载25次)
1位全加器的vhdl设计
通过两个半加起实现
A full adder of VHDL design increases since the adoption of two and a half to achieve (2008-12-15, VHDL, 109KB, 下载4次)
该代码是布斯乘法器代码，用于了解布斯算法，本人也是初学者。
err (2008-12-14, VHDL, 91KB, 下载20次)
这是一个利用MAX PULL 制作的VHDL的四位全加器的程序 如果有需要仿真图的 请叫站长联系我
This is a MAX PULL using VHDL produced four full-adder process simulation map, if necessary please contact me call station (2008-06-14, VHDL, 1KB, 下载4次)
VHDL实现四位全加器，适合初学者，源程序下载
VHDL realization of four full adder, suitable for beginners, the source code download (2008-04-29, VHDL, 110KB, 下载17次)