-数字前面加0x表示该数是十六进制的数，0x00就是十六进制的00--//
//--P0口一共有8个IO口，即从P0.0到P0.7，而0x00二进制就是0000 0000
Before the number, add 0 to indicate that the number is hexadecimal, and 0x00 is hexadecimal (2020-01-05, VHDL, 298KB, 下载0次)
俄罗斯方块verilog程序代码，实现经典游戏俄罗斯方块的程序
有参考意义
可以运行
Russian Tetris Verilog Program Code to Realize the Program of the Classic Game Russian Tetris
It has reference significance.
Can run (2019-04-18, VHDL, 7KB, 下载1次)
布斯乘法器设计源码。。功能完善，modelsim仿真通过
Booth Multiplier source. . Perfect function, modelsim simulation through (2016-06-23, VHDL, 3KB, 下载6次)
8位全加器，为EDA的第一个实验，由半加器和或门组成
8 full adder bit EDA experiment first simple experiment, through the OR gate constructed with half-adder (2015-02-07, VHDL, 255KB, 下载1次)
用 VHDL 语言设计一半加器电路，然后用元件例化（COMPONENT）语句调用两个半加器电路，用结构描述实现一个全加器。
Design using VHDL half-adder circuit, and then use component instantiation (COMPONENT) statement invokes two half adder circuit, with the structure described in the realization of a full adder. (2014-09-16, VHDL, 98KB, 下载3次)
4位全加器由3个模块构成。首先，通过实例引用基本门级元件xor、and定义底层的半加器模块halfadder，接着实例引用两个半加器模块halfadder和一个基本或门元件or组合成为全加器模块fulladder，最后实例引用4个1位的全加器模块fulladder构成4位全加器的顶层模块
4 full adder by the three modules. First, the basic gate-level component instance references xor, and define the underlying half-adder module halfadder, then cite two examples of half-adder module halfadder and a base or gate element or combination of a full adder module fulladder, the last instance references 4 a one of the full adder module fulladder constitute four full adder top module (2013-08-18, VHDL, 393KB, 下载2次)
在赛灵思软件ISE上实现的ＡＥＳ加解密算法，并且在ＭＯＤＥＬＳＩＭ上仿真。希望对你有所帮助
The Xilinx software ISE AES encryption and decryption algorithms, and simulation MODELSIM on. I hope for your help (2013-04-15, VHDL, 79KB, 下载8次)
巴特沃斯滤波器的Verilog实现，基于matlab
Butterworth filter Verilog implementation based on matlab (2012-12-01, VHDL, 6KB, 下载16次)
介绍了verilog HDL语言对AES算法进行数据加解密。
Introduced the verilog HDL language to AES algorithm for data encryption and decryption. (2012-11-05, VHDL, 76KB, 下载81次)
ISE工程 包含各种基本部件 全加器 寄存器 解码器等等
The ISE project includes various basic components of the full adder register decoder (2012-09-01, VHDL, 2458KB, 下载5次)
EDA实验中的全加器的VHDL语言的实现，包含半加器、全加器、JK触发器、D触发器以及50m分频的源程序
EDA test full adder in VHDL language implementation, including the half adder, full adder, JK flip-flop, D flip-flop and the frequency of the source 50m (2011-05-03, VHDL, 1286KB, 下载7次)
曼切斯特编码器的有一种verilog实现，附带有仿真波形，和时序分析
verilog (2010-12-20, VHDL, 10KB, 下载24次)
布斯算法 LMS算法
布斯算法 LMS算法
布斯算法 LMS算法
布斯算法 LMS算法
Booth algorithm LMS algorithm LMS operator operator Fabu Si Fa Busi algorithm LMS algorithm LMS algorithm Operator Fa Busi (2010-05-11, VHDL, 45KB, 下载39次)
整数模加器的一种硬件设计方法,在深入分析模加运算的实现基础上，提出了一种模加运算的实现方案，并论证了该方案的正确性。基于这种实现方案．设计并验证了一块实现l6位模加运算的逻辑电路，仿真结果表明了电路的正确性和设计方案的可行性。
A hardware design method of integer modular adder. (2010-01-14, VHDL, 709KB, 下载7次)
加德罗域乘法器提供了一种新型的乘法器设计模式
Multiplier加德罗domain to provide a new design of the multiplier model (2009-07-09, VHDL, 2KB, 下载9次)
用VHDL语言设计四位全加器，有低位进位和高位进位。
VHDL language with four full-adder design, there are low and the high binary binary. (2009-04-16, VHDL, 2KB, 下载26次)
1位全加器 可以进行1位的二进制码的加法 想进行改进 改为4位或8位的全加器代码
A full adder can be an addition of the binary code would be changed to improve the 4 or 8-bit full adder code (2009-04-15, VHDL, 2KB, 下载42次)
8位全加器的VHDL语言描述，有需要的顶一下。
8-bit full adder described in the VHDL language, there is a need to click the top. (2009-04-04, VHDL, 115KB, 下载7次)
曼彻斯特编码实现，verilog HDL 做的，我也是从网上下的
Manchester encoding to achieve, verilog HDL to do, I am also from the Internet under (2008-11-30, VHDL, 1KB, 下载169次)
曼彻斯特编码的VHDL源程序?顾固乇嗦氲腣HDL源程序
Manchester-coded VHDL source code? Gu SOLID乇winded heavy atmosphere腣HDL source (2008-07-12, VHDL, 10KB, 下载39次)