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按平台查找All VHDL(944) 

[嵌入式/单片机/硬件编程] Mips54

米普斯54,,
Mips54,, (2017-07-18, VHDL, 0KB, 下载0次)

http://www.pudn.com/Download/item/id/1688839280645424.html

[VHDL/FPGA/Verilog] 曼彻斯特编码

标准曼彻斯特编码程序,通过仿真测试正常。
the code VHDL software and simulation (2020-03-02, VHDL, 750KB, 下载0次)

http://www.pudn.com/Download/item/id/1583154950946081.html

[VHDL/FPGA/Verilog] quartuswork

vhdl入门实例,一位全加器和一位半加器的quartus9.1程序,可直接运行
VHDL entry examples, a full adder and a half adder quartus9.1 program, can be run directly (2017-10-29, VHDL, 2571KB, 下载1次)

http://www.pudn.com/Download/item/id/1509258962916340.html

[其他] xor8b

实现8位全加器,为初学者提供参考,对VHDL语言有一定了解
It's a addler of 8 bits,which is designed for new learners (2017-07-11, VHDL, 93KB, 下载1次)

http://www.pudn.com/Download/item/id/1499777058319879.html

[VHDL/FPGA/Verilog] fulladder

一位全加器的设计,基于VHDL语言的,顶层为语言
full adder (2016-04-18, VHDL, 155KB, 下载1次)

http://www.pudn.com/Download/item/id/1460979794232251.html

[VHDL/FPGA/Verilog] lab5

用Verilog 实现的计数器和简单的Verilog全加器。 同时也包含了最基础的计数器和全加器的Verilog写法
counters in verilog (2014-10-31, VHDL, 2644KB, 下载2次)

http://www.pudn.com/Download/item/id/2645722.html

[VHDL/FPGA/Verilog] Four-binary-adder

熟悉 VHDL 语言的模块化设计,了解元件例化和打包调用语句。用 VHDL 语言设计一半加器电路,然后用元件例化(COMPONENT)语句调用两个半加器电路,用结构描述实现一个全加器。
The modular design of VHDL language familiar to understand the components and packing cases call statement. Design using VHDL half-adder circuit, and then use component instantiation (COMPONENT) statement invokes two half adder circuit, with the structure described in the realization of a full adder. (2014-09-16, VHDL, 3375KB, 下载2次)

http://www.pudn.com/Download/item/id/2620628.html

[VHDL/FPGA/Verilog] md

曼彻斯特编码的实现,Verilog模型。测试通过!!!
FPGA Verilog Module. (2013-12-12, VHDL, 1KB, 下载7次)

http://www.pudn.com/Download/item/id/2424364.html

[VHDL/FPGA/Verilog] Manchester

运行于Altera Cyclone FPGA平台,由VHDL编写的NRZ到曼彻斯特编码和曼彻斯特编码到NRZ解码程序。
Running on Altera Cyclone FPGA platform, consisting in VHDL coding NRZ to Manchester and Manchester encoding to NRZ decoding process. (2013-09-19, VHDL, 323KB, 下载30次)

http://www.pudn.com/Download/item/id/2358527.html

[VHDL/FPGA/Verilog] manchester

Verilog HDL 曼彻斯特编解码,16位并口的曼彻斯特编解码
manchester decode and encode Verilog (2013-05-16, VHDL, 2KB, 下载23次)

http://www.pudn.com/Download/item/id/2245569.html

[VHDL/FPGA/Verilog] VHDL

带有CDR和曼彻斯特编解码的串行接口,代码编译仿真成功过
Control Link Serial Interface with Manchester and CDR (2012-05-31, VHDL, 13KB, 下载23次)

http://www.pudn.com/Download/item/id/1896615.html

[VHDL/FPGA/Verilog] Ten-binary-clock-

数字时钟 十二进制的 年月日可自加
digital clock (2011-12-13, VHDL, 433KB, 下载8次)

http://www.pudn.com/Download/item/id/1729248.html

[VHDL/FPGA/Verilog] addr4

可以实现四位全加器,使用四个全加器串联的方式,不是快速进位位的方式
Can achieve four full adder, full adder using four series were not as fast carry bit of the way (2011-10-28, VHDL, 3KB, 下载5次)

http://www.pudn.com/Download/item/id/1682428.html

[VHDL/FPGA/Verilog] TEST

I2C总线的实现,一个基于计数器的加法器。其中使用三个寄存器来实现计数器的功能,再由两个半半加器实现全加器额功能。
realize the inter-integrated circuit bus (2011-05-03, VHDL, 526KB, 下载5次)

http://www.pudn.com/Download/item/id/1515603.html

[VHDL/FPGA/Verilog] verilog_Manchester

曼彻斯特码编码电路,在工业电路中有较好的抗干扰性,而且编码电路简单,容易在FPGA上实现
Manchester encoding circuit, the circuit in the industry in a better anti-interference, and the coding circuit is simple, easily implemented on FPGA (2011-01-06, VHDL, 1KB, 下载11次)

http://www.pudn.com/Download/item/id/1404709.html

[VHDL/FPGA/Verilog] mcsdte

FPGA嵌入式项目实战,曼彻斯特编码器与译码器
FPGA embedded project combat, Manchester encoder and decoder (2010-11-02, VHDL, 182KB, 下载54次)

http://www.pudn.com/Download/item/id/1334217.html

[VHDL/FPGA/Verilog] ManchesterEncoding

FPGA实现的曼切斯特编码 VHDL语言
Manchester Encoding based on FPGA (2010-05-29, VHDL, 332KB, 下载48次)

http://www.pudn.com/Download/item/id/1193553.html

[VHDL/FPGA/Verilog] ALU

算术逻辑部件的verilog代码,它能够实现半加器、全加器、比较、按位与、按位或、按位异或、加一、减一的操作
Arithmetic logic unit of the verilog code, it can achieve half adder, full adder, compare, bitwise and, bitwise or, bitwise xor, plus one, minus one operation (2010-04-23, VHDL, 166KB, 下载33次)

http://www.pudn.com/Download/item/id/1140243.html

[VHDL/FPGA/Verilog] AES_RTL

使用Verilog HDL 實現AES硬體加解密
Realize the use of Verilog HDL hardware AES encryption and decryption (2008-07-13, VHDL, 15KB, 下载245次)

http://www.pudn.com/Download/item/id/509700.html

[VHDL/FPGA/Verilog] manchester_verilog

曼彻斯特编解码Verilog代码 非常好的 速度快,而且资源占用少。
Manchester codec Verilog code very good speed, but also occupy less resources. (2008-06-13, VHDL, 10KB, 下载151次)

http://www.pudn.com/Download/item/id/489277.html
总计:944