verilog,arty z7 10,维瓦多
verilog, arty z7 10 , vivado (2024-02-12, VHDL, 0KB, 下载0次)
半加器、全加器、多路复用器、编码器、解码器、触发器、锁存器、寄存器、FSM和微型计算器项目。,
Half Adder, Full Adder, Multiplexer, Encoder, Decoder, Flip Flop, Latch, Register, FSM and Mini-Calculator project., (2018-07-19, VHDL, 0KB, 下载0次)
用verilog语言开发俄罗斯方块小游戏
Developing Tetris game with Verilog language (2020-11-27, VHDL, 46721KB, 下载2次)
用verilog语言编写的全加器模块代码,在ISE软件环境下编译开发,希望对大家有所帮助!
With verilog language full adder module code in ISE software compiler development environment, we want to help! (2016-04-13, VHDL, 151KB, 下载2次)
8位加法器源代码,vivado实现编写。
8 adder Source, vivado achieve write. (2015-12-01, VHDL, 451KB, 下载21次)
基于VHDL语言的HD4069曼彻斯特编码器实现
Based on VHDL HD4069 Manchester encoder implementation (2013-01-29, VHDL, 168KB, 下载15次)
基于FPGA的俄罗斯方块VHDL逻辑代码,通过VGA显示在液晶屏幕上,基本功能完全实现
VHDL logic code Tetris FPGA-based VGA display on the LCD screen, the basic functions of the full realization of (2012-11-06, VHDL, 3759KB, 下载77次)
8*8点阵实现俄罗斯方块功能,左移右移以及消行
8* 8 dot matrix Tetris (2012-06-12, VHDL, 1076KB, 下载6次)
基于FPGA 的全加器设计。应用软件是Qartaus 2
full_adder design (2012-04-24, VHDL, 250KB, 下载4次)
八位全加器的源代码,用verilog编写,没有附带测试程序
eight summury (2011-12-05, VHDL, 2KB, 下载4次)
PS/2键盘加DDS的verilog 设计
PS/2 keyboard plus the verilog design DDS (2011-08-18, VHDL, 1923KB, 下载2次)
LCD1602控制器,液晶显示控制模块。VHDL代码。comment是自己加的
LCD1602 controller (2011-05-23, VHDL, 2KB, 下载4次)
以ISE为平台,用Verilog编写的32位全加器模块,只需在Top模块中调用即可
The ISE as a platform, written with Verilog 32-bit full adder module, simply call the module to Top (2011-05-21, VHDL, 2KB, 下载5次)
lcd12864 全屏显示
汉字加字符
lcd12864 full screen characters plus characters (2010-05-28, VHDL, 1KB, 下载10次)
布斯乘法器 这种特殊的乘法器供给需要使用的人使用
Booth multiplier (2010-05-19, VHDL, 2KB, 下载1次)
算数逻辑单元,实现算数加、减,加1、减1运算和逻辑与、或、非和传递
Arithmetic logic unit, to achieve arithmetic add, subtract, plus one, minus one operation and logical AND, OR, and transmission of non- (2009-11-04, VHDL, 296KB, 下载17次)
一个半加器,具有进位和位数相加的基本功能,可作为全加器的基本模块
One and a half adder with binary and the sum of the basic functions of the median, full adder can be used as the basic module (2009-08-11, VHDL, 72KB, 下载2次)
VHDL编写计算器,功能包括:加,减,乘,除。通过keypad输入及输出
Calculator written with VHDL (2009-07-11, VHDL, 307KB, 下载85次)
八位加法器的原理图实现方法和一位半加器 全加器的原理图实现
Eight adder schematic diagram of the method and a half adder full adder schematic diagram of the realization of (2009-06-07, VHDL, 268KB, 下载4次)
4 级流水方式的8 位全加器。。。。。。
Way flow of 4 full adder 8. . . . . . (2009-04-29, VHDL, 1KB, 下载3次)