[VHDL/FPGA/Verilog] Programs-VHDL
[https:www.youtube.com watch v=FzsPFgjVV7Q&ab_channel=FarFromAlaska-主题]（https:www.youtube.com watch v=FzspfgjV57Q&ab_channel=FarFrom阿拉斯加-主题），
[https: www.youtube.com watch v=FzsPFgjVV7Q&ab_channel=FarFromAlaska- Topic](https: www.youtube.com watch v=FzsPFgjVV7Q&ab_channel=FarFromAlaska- Topic), (2023-09-23, VHDL, 0KB, 下载0次)
[其他] adder
应用半加器实现一位全加器再实现 八位全加器
Implementation of a full adder by half adder and eight bit full adder (2018-09-05, VHDL, 5678KB, 下载0次)
[VHDL/FPGA/Verilog] AES
AES代码 加解密代码 systemverilog编程
AES code (2015-01-06, VHDL, 991KB, 下载7次)
[VHDL/FPGA/Verilog] h_adder
半加器VHDL代码，包含所有文件，较清晰
Half adder VHDL code, including all documents, clearer (2013-05-17, VHDL, 107KB, 下载3次)
[VHDL/FPGA/Verilog] fadder
全加器，由2个半加器构成的VHDL语言，有进位位。
failed to translate (2013-05-07, VHDL, 19KB, 下载3次)
[VHDL/FPGA/Verilog] AES__veriloghdl
RAS加解密模块，实现ras加密，解密功能。包括顶层文件，verilog代码实现
RAS Encryption and decryption (2013-04-15, VHDL, 19KB, 下载17次)
[VHDL/FPGA/Verilog] full_adder
全加法器，全加器描述，由两个半加器连接而成
full adder (2012-11-09, VHDL, 1KB, 下载4次)
[VHDL/FPGA/Verilog] adder
涉及半加器与全加器的电路连线图模块。非语言编写。
FPGA-verilog,full_adder and half_adder. (2011-12-15, VHDL, 199KB, 下载2次)
[VHDL/FPGA/Verilog] h_adder
半加器的实现，利用VHDL语言实现半加器的运算
Half adder implementation using VHDL language and a half-adder operation (2011-12-13, VHDL, 40KB, 下载3次)
[VHDL/FPGA/Verilog] avs_aes_latest[1].tar
数字加解密模块的设计
Digital encryption and decryption module design (2011-11-28, VHDL, 408KB, 下载3次)
[VHDL/FPGA/Verilog] full_add
全加器，基于原理图设计的全加器。经过时序仿真验证
Full adder, based on the schematic design of the full adder. After timing simulation (2011-06-03, VHDL, 8KB, 下载5次)
[VHDL/FPGA/Verilog] example3
加/减法计数器：本程序实现的是一个加/减8进制计数器
Add/down counter: The program implementation is a plus/minus 8 binary counter (2011-03-11, VHDL, 26KB, 下载4次)
[VHDL/FPGA/Verilog] VHDL
译码器。半加器，全加器。。。包括源程序和仿真波形
Decoder. Half adder, full adder. . . Including the source and the simulation waveform (2010-10-23, VHDL, 341KB, 下载9次)
[VHDL/FPGA/Verilog] music_yetong1
电子琴加音乐播放功能，电子琴加音乐播放功能，电子琴加音乐播放功能，电子琴加音乐播放功能，
music play (2010-06-17, VHDL, 485KB, 下载7次)
[VHDL/FPGA/Verilog] EDA
课程实验，VHDL语言实现半加器全加器，频率计等，共四个
eda (2010-01-14, VHDL, 2328KB, 下载12次)
[VHDL/FPGA/Verilog] ghjk
十进制加法器 示范的的游侠的序号的的剑客骄傲 到家了库文件发动机阿拉斯加法律
Decimal adder demonstration of the Ranger of the serial number of the swordsman proud home of the library file engine Alaska law (2009-12-14, VHDL, 2KB, 下载7次)
[编辑器/阅读器] 2008619105258431
九个输入，一个输出，实现四位全加器，四位全加器的功能
9 input, 1 output, to achieve four full-adder, four full-adder function (2009-09-17, VHDL, 941KB, 下载4次)
[VHDL/FPGA/Verilog] f_adder8
fpga八位全加器(vhdl语言),由画图法制作,将八个一位全加器(由一位半加器组成)组合制成
fpga eight full adder (vhdl language) (2009-08-13, VHDL, 269KB, 下载8次)
[其他] add4bit
一位全加器的VHDL源码与TEST BENCH.XILINX下通过
A full adder and the VHDL source code through TEST BENCH.XILINX (2009-07-20, VHDL, 794KB, 下载49次)
[VHDL/FPGA/Verilog] VHDL03
全加器仿真程序代码，本人亲自测试，代码简单，安全无毒。放心下载和使用。
Full adder simulation code, I personally tested the code simple, safe non-toxic. Ease to download and use. (2009-05-26, VHDL, 1KB, 下载43次)